JPS60745A - Apparatas for manufacturing semiconductor wafer - Google Patents

Apparatas for manufacturing semiconductor wafer

Info

Publication number
JPS60745A
JPS60745A JP58108128A JP10812883A JPS60745A JP S60745 A JPS60745 A JP S60745A JP 58108128 A JP58108128 A JP 58108128A JP 10812883 A JP10812883 A JP 10812883A JP S60745 A JPS60745 A JP S60745A
Authority
JP
Japan
Prior art keywords
base
flatness
semiconductor wafer
cutting edge
measuring device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58108128A
Other languages
Japanese (ja)
Inventor
Yoshisato Hosoki
細木 芳悟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58108128A priority Critical patent/JPS60745A/en
Publication of JPS60745A publication Critical patent/JPS60745A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices

Landscapes

  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体ウェハの製造装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor wafer manufacturing apparatus.

〔発明の背景技術〕[Background technology of the invention]

従来、半導体ウニ・・は、チョクラルスキー法等で得ら
れた円柱状の単結晶体を、所定の肉厚のものにスライス
加工して製造されている。このようなスライス加工処理
を行う半導体ウニ・・の製造装置は、環状基盤の中央部
に形成された貫入孔の内周縁部に刃先部を設けて、貫入
孔内に挿入された単結晶体に、円盤を回転させ冷却水を
流しながら刃先部番押し付は名ことによりスライス加工
を施すようになっている。而して、スライス加工処理は
、予め、円盤の外周細部に設けられた基盤張設がルトに
よシ、基盤を水平状態に張設した後に行っている。この
基盤の張≠後の水平状態、つまり、基盤の平坦度は、調
輿された基盤張設ゲルトに対向する刃先部に、ローラー
付ダイヤルグー・ゾを当設して中心部から刃先部までの
距離の変動を調べることにより行っている。
Conventionally, semiconductor sea urchins have been manufactured by slicing a cylindrical single crystal obtained by the Czochralski method or the like into pieces of a predetermined thickness. Semiconductor sea urchin manufacturing equipment that performs such slicing processing has a cutting edge on the inner peripheral edge of a penetration hole formed in the center of the annular base, and a cutting edge is provided at the inner peripheral edge of the penetration hole formed in the center of the annular base to slice the single crystal body inserted into the penetration hole. The slicing process is performed by rotating the disk and pressing the number on the cutting edge while flowing cooling water. The slicing process is performed after the base plate provided on the outer circumference of the disc has been stretched horizontally. The horizontal state of the base after tensioning, that is, the flatness of the base, is determined by placing a dial goo with a roller on the cutting edge facing the adjusted base tensioning gel from the center to the cutting edge. This is done by examining the variation in the distance between.

〔背景技術の問題点〕[Problems with background technology]

このようにローラ付ダイヤルダージを用いて張設後の基
盤の平坦度を測定するようにした半導体ウニ・・の製造
装置では、スライス加工処理前の基盤の平坦度は、第1
図(A) ([3) (C) (D)及び第2図(ト)
(B) (C)に示す通シである。
In the semiconductor sea urchin manufacturing equipment that uses a dial dirge with a roller to measure the flatness of the substrate after being stretched, the flatness of the substrate before the slicing process is measured by the first
Figures (A) ([3) (C) (D) and Figure 2 (G)
(B) This is the passage shown in (C).

第3図は、張設された基盤1の平面図を示している。同
図中2は、ダイヤモンドブレード等からなる刃先部であ
る。第1図(局は、第3図に示す基盤1の中心点3から
所定の外周方向(ぺ(仮に下方向とする。)に沿う平坦
度を中心点3からの距離5111111(Ll)、50
m(L2)、13011111(Ll)の各地点につい
て、基準面からの変位量に従って示したものである。こ
の下方向(4)については、中心点3から外周方向に遠
ざかるに従って、基盤面が隆起していることが判る。同
様に、第1図(日は、中心点3から左方向(119の外
周に向う各地点(Ll )(L2 )(Ls )の起伏
を示し、外周に向って基準面から次第に低くなっている
ことが判る。第1図1c)は、同様に中心点3から上方
向(C’lに沿った基盤面の起伏を示し、外周に向って
基準面から次第に高くなっていることが判る。更に、第
1図(0は、中心点3が右方向(6)に沿う場合で、外
周に向うに従って基準面から次第に低くなっていること
が判る。また、第2図(Atは、基盤10周方向に沿う
刃先部2から5瓢の地点の起伏を示し、第2図(B)は
、刃先部3から50瓢の地点の周、方向に沿う起伏を示
し、第2図(Q /I′i、130關の地点の周方向に
沿う起伏を示している。これらの図から明らかな如く、
外周に近い領域はど周方向に沿う起伏が多いことが判る
FIG. 3 shows a plan view of the stretched base 1. 2 in the figure is a cutting edge portion made of a diamond blade or the like. Fig. 1 (The flatness is measured from the center point 3 of the base 1 shown in Fig. 3 along a predetermined outer peripheral direction (temporarily downward direction) from the distance 5111111 (Ll), 50
Each point of m (L2) and 13011111 (Ll) is shown according to the amount of displacement from the reference plane. Regarding the downward direction (4), it can be seen that the base surface rises as it moves away from the center point 3 in the outer circumferential direction. Similarly, Figure 1 (day) shows the undulations of each point (Ll) (L2) (Ls) from the center point 3 to the left (119), and gradually becomes lower from the reference plane toward the outer periphery. It can be seen that Fig. 1c) similarly shows the undulations of the base surface from the center point 3 upward (along C'l), and it can be seen that it gradually becomes higher from the reference plane toward the outer periphery. , Fig. 1 (0 is the case where the center point 3 is along the right direction (6), and it can be seen that it gradually becomes lower from the reference plane toward the outer circumference. Also, Fig. 2 (At is the case where the center point 3 is along the right direction (6) Figure 2 (B) shows the undulations along the circumference and direction at a point 50 gourds from the cutting edge part 2, and Figure 2 (B) shows the undulations along the circumference and direction at a point 50 gourds from the cutting edge part 3. It shows the undulations along the circumferential direction at the point at 130 degrees.As is clear from these figures,
It can be seen that the area near the outer periphery has many undulations along the circumferential direction.

従来の半導体ウェハの製造装置では、平坦度の調節後で
あっても第1図(Aω) (C) (1))及び第2図
(ハ))の)(C)に示す如く基盤に大きな起伏がある
。このため従来の半導体ウェノ・の製造装置によって半
導体単結晶体からスライス加工して得られたウェハの反
シの状態を調べると、第4図に特性線(1)にて示す如
く、極めて大きなばらつきを示している。その結果、歩
留を低下する問題があった。
In conventional semiconductor wafer manufacturing equipment, even after adjusting the flatness, there is a large amount of damage to the substrate as shown in (C) in Figure 1 (Aω) (C) (1)) and Figure 2 (C)). There are ups and downs. For this reason, when we examine the state of the wafers obtained by slicing from semiconductor single crystals using conventional semiconductor wafer manufacturing equipment, we find that there are extremely large variations, as shown by characteristic line (1) in Figure 4. It shows. As a result, there was a problem of lower yield.

〔発明の目的〕[Purpose of the invention]

本発明は、反りの小さい平坦度の高いウエノ・を容易に
製造して歩留シの向上を達成した半導体単結晶切断装置
を提供することをその目的とするものである・ 〔発明の概要〕 本発明は、刃先部を支持する基盤の平坦度を測定する平
坦度測定器を設けたことにょシ、反シのない平坦度の高
いウェハを容易に製造して歩留シの向上を達成した半導
体単結晶切断装置である。
An object of the present invention is to provide a semiconductor single crystal cutting device that can easily produce a highly flat wafer with little warpage and achieve an improved yield. [Summary of the Invention] The present invention provides a flatness measuring device to measure the flatness of the base supporting the cutting edge, thereby easily manufacturing wafers with high flatness without any rips, and achieving an improvement in yield. This is a semiconductor single crystal cutting device.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例につbて図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第5図囚(B)は、本発明の一実施例の概略構成を示す
説明図である。図中10は、基台である。
FIG. 5(B) is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. 10 in the figure is a base.

基台10上には、第6図に示す如き環状円盤からなる基
盤11が設けられている。基盤11の外周縁部上には、
例えば締付はダルトからなる基盤張設用部材12が所定
間隔を設けて配置されている。基盤11の中心部には、
被処理体である単結晶体13が挿入される貫入孔14が
形成されている。貫入孔14の内周縁部には、ダヤモン
ドブレード等からなる刃先部15が形成されている。基
盤11の上方には、平坦度測定器16が周方向に沿って
移動自在に設けられている。基盤11は、図示しない駆
動機構によって直径方向に自在に移動するようになって
いる。
A base 11 made of an annular disk as shown in FIG. 6 is provided on the base 10. As shown in FIG. On the outer peripheral edge of the base 11,
For example, for tightening, base-stretching members 12 made of dart are arranged at predetermined intervals. In the center of the base 11,
A penetration hole 14 is formed into which a single crystal body 13, which is an object to be processed, is inserted. A cutting edge portion 15 made of a diamond blade or the like is formed at the inner peripheral edge of the penetration hole 14 . A flatness measuring device 16 is provided above the base 11 so as to be movable along the circumferential direction. The base 11 is configured to freely move in the diametrical direction by a drive mechanism (not shown).

ここで、平坦度測定器16は、例えば、レーザ、音波等
の距離測定器で構成されておシ、基盤面と平坦度測定器
16間の距離を測定して、基盤面の平坦度2ii−調べ
るようになっている。
Here, the flatness measuring device 16 is configured with a distance measuring device such as a laser or a sound wave, and measures the distance between the base surface and the flatness measuring device 16 to determine the flatness of the base surface. I'm starting to look into it.

このように構成された半導体ウニ・・の製造装置20に
よれば、第5晶示す如く、弛んだ秋、□ 態にある基盤11を基盤張設用部材12を例ガば六角レ
ンチ21で締め付けることにより、緊張した状態に張シ
上げる。この基盤張設操作は、基盤11の全周に亘って
行う。基盤張設操作の完了は、第5図(B)に示す如く
、締付けを行っている基盤張設部材12と貫入孔14の
中心点を結ぶ直線に沿って基盤11の平坦度を、平坦度
測定器16によって測定して所定値に達したところで確
認する。然る後、貫入孔14内に被処理体である円柱状
の単結晶体13を挿入し、基盤11を回転させ冷却水を
流しながら直径方向に沿って移動することによシ、単結
晶体13にスライス加工を施す。その結果、所定の肉厚
の半導体ウェハを得る。
According to the semiconductor manufacturing apparatus 20 configured in this way, as shown in the fifth crystal, the board 11 in the slack state is tightened with the board tensioning member 12 using, for example, the hexagonal wrench 21. This puts you in a tense state. This base laying operation is performed over the entire circumference of the base 11. When the base tensioning operation is completed, as shown in FIG. It is measured by the measuring device 16 and confirmed when it reaches a predetermined value. After that, the cylindrical single crystal body 13, which is the object to be treated, is inserted into the penetration hole 14, and the single crystal body is removed by rotating the base 11 and moving it along the diameter direction while flowing cooling water. 13 is subjected to slicing processing. As a result, a semiconductor wafer with a predetermined thickness is obtained.

このようにこ9半導体ウェハの製造装置2゜によれば、
平坦度測定器16によって基盤11の平坦度を観察しな
がら基盤張設操作を行っているので、第7図(A)ω)
 (c) (o)及び第8図体)申)0に示す如く、ス
ライス加工処理前の基盤11の平坦度は極めて高い。こ
こで、第7図(A) (B) (C)(6)は、基盤1
1の中心点23から下方向(局、下方向(C)、左方向
(n)、右方向(口に沿う平坦度を、刃先部15から5
111111(Ll)、50 tan (Lx )、1
30wm(L3)の地点をもとに調べたものである(第
6図参照)。直径方向についての平坦度は何れの方向(
AI・・・(D)についても極て高い平坦度に設定され
ていることが判る。また、第8図囚小)(C)は、L1
地点、L2地点、L3地点の各々の周方向に沿う平坦度
を調べたものである。何れのものも第3図に示す従来の
ものの場合に比べて、遥かに高い平坦度に設定されてい
ることが判る。
In this way, according to this 9 semiconductor wafer manufacturing apparatus 2°,
Since the base plate installation operation is performed while observing the flatness of the base 11 using the flatness measuring device 16, the flatness of the base 11 is observed using the flatness measuring device 16, so the flatness of the base 11 is measured using the flatness measuring device 16.
As shown in (c) (o) and Figure 8), the flatness of the substrate 11 before the slicing process is extremely high. Here, FIG. 7 (A) (B) (C) (6) shows the base 1
1 from the center point 23 (downward (C), leftward (n), rightward (flatness along the mouth) from the cutting edge part 15 to 5
111111 (Ll), 50 tan (Lx), 1
This is a survey based on the point at 30 wm (L3) (see Figure 6). The flatness in the diametrical direction is
It can be seen that AI...(D) is also set to an extremely high degree of flatness. In addition, Figure 8 Prisoner Small) (C) is L1
The flatness along the circumferential direction of each point, L2 point, and L3 point was investigated. It can be seen that all of the flatnesses are set to a much higher degree of flatness than the conventional one shown in FIG.

このように極めて高い平坦度に張設された基盤11によ
シスライス加工されて得られた半導体ウェハの反シ状態
は、第4図に特性線(II)にて示す如く、従来のもの
に比べて、遥かに小さい値であることが判る。
As shown by the characteristic line (II) in FIG. 4, the anti-chip state of the semiconductor wafer obtained by slicing the substrate 11 stretched to an extremely high degree of flatness is different from that of the conventional one. It can be seen that the value is much smaller.

その結果、この半導体ウェハの製造装置20によれば、
基盤11を高い平坦度で張設してスライス加工の際の抵
抗を小さくし、刃先部15の寿命を長くできる。また、
ローラ付グイヤルグージが不要となシ、作業性を向上さ
せることができる。しかも、反シの小さい半導体ウェハ
を容易に製造して歩留F)k向上させることができる。
As a result, according to this semiconductor wafer manufacturing apparatus 20,
By stretching the base 11 with high flatness, the resistance during slicing can be reduced, and the life of the cutting edge portion 15 can be extended. Also,
There is no need for a gouillage with a roller, and work efficiency can be improved. Moreover, it is possible to easily manufacture semiconductor wafers with a small cross-section and improve the yield F)k.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る半導体単結晶切断装置
によれば、反シのない平坦度の高いウェハを容易に製造
して歩留シの向上を達成できるものである。
As explained above, according to the semiconductor single crystal cutting apparatus according to the present invention, it is possible to easily produce wafers with high flatness and no undulations, thereby achieving an improvement in yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第7図は、基盤の直径方向の平坦度を示す特
性図、第2図及び第8図は、基盤の周方向の平坦度を示
す特性図、第3図及び第6図は、基盤の平面図、第4図
は、半導体ウェノ・の反りと枚数の関係を示す特性図、
第5図は、本発明の一実施例゛の概略構成を示す説明図
である。 10・・・基台、11・・・基盤、12・・・基盤調節
部材、13・・・単結晶体、14・・・貫入孔、150
0.刃先部、16・・・平坦度測定器、と・・・半導体
ウェハの製造装置、21・・・六角レンチ、23・・・
中心点O
Figures 1 and 7 are characteristic diagrams showing the flatness of the base in the diametrical direction, Figures 2 and 8 are characteristic diagrams showing the flatness of the base in the circumferential direction, and Figures 3 and 6 are characteristic diagrams showing the flatness of the base in the circumferential direction. , a plan view of the substrate, and FIG. 4 is a characteristic diagram showing the relationship between warpage and number of semiconductor wafers.
FIG. 5 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Base, 11... Base, 12... Base adjustment member, 13... Single crystal, 14... Penetration hole, 150
0. Blade edge portion, 16... Flatness measuring device, and... Semiconductor wafer manufacturing equipment, 21... Hexagonal wrench, 23...
center point O

Claims (1)

【特許請求の範囲】[Claims] 譲状円盤からなる基盤と、該基盤の中心部に形成された
被処理体の貫入孔と、該貫入孔内に臨む前記基盤の内周
縁部に形成された刃先部と、前記基盤の外周縁部に所定
間隔で設けられた基盤張設用部材と、前記基盤の表面に
対向し、かつ、周方向に沿って移動自在に設けられた平
坦度測定器と、前記基盤を直径方向に沿って移動する駆
動機構とを具備することf、%徴とする半導体ウェノ・
の製造装置。
A base made of a yield-shaped disk, a penetration hole for the object to be processed formed in the center of the base, a cutting edge formed at the inner peripheral edge of the base facing into the penetration hole, and an outer peripheral edge of the base a flatness measuring device that faces the surface of the base and is movable along the circumferential direction; A semiconductor wafer having a moving drive mechanism.
manufacturing equipment.
JP58108128A 1983-06-16 1983-06-16 Apparatas for manufacturing semiconductor wafer Pending JPS60745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58108128A JPS60745A (en) 1983-06-16 1983-06-16 Apparatas for manufacturing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58108128A JPS60745A (en) 1983-06-16 1983-06-16 Apparatas for manufacturing semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS60745A true JPS60745A (en) 1985-01-05

Family

ID=14476640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58108128A Pending JPS60745A (en) 1983-06-16 1983-06-16 Apparatas for manufacturing semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS60745A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683176A (en) * 1983-08-15 1987-07-28 Nihonshinku Gijutsu Kabushiki Kaisha Optical magnetic recording member
JPH04216012A (en) * 1990-12-13 1992-08-06 Tokyo Seimitsu Co Ltd Cutting method for slicing machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683176A (en) * 1983-08-15 1987-07-28 Nihonshinku Gijutsu Kabushiki Kaisha Optical magnetic recording member
JPH04216012A (en) * 1990-12-13 1992-08-06 Tokyo Seimitsu Co Ltd Cutting method for slicing machine

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