JPS6074877A - Reproducing circuit of syncronizing signal - Google Patents

Abstract

PURPOSE:To reduce the phase shift of a vertical synchronizing pulse and to reduce an error by generating a mask pulse from a horizontal synchronizing process mask circuit to stop the actuation of a phase wave detecting circuit for a period of a vertical synchronizing signal and equivalent pulses before and after said synchronizing signal. CONSTITUTION:The oscillation output of a voltage control oscillator is divided by 1/16 divider 31 of a synchronizing signal reproducing circuit, and this division output is divided by a 1/2 divider 32 to produce horizontal synchronizing pulses. At the same time, the outputs of the divider 31 are counted by a vertical counter 33. Then the vertical synchronizing pulses are produced from a vertical synchronism detecting circuit 34. The output of the circuit 34 is applied to a reset pulse producing circuit 35, and the counter 33 is reset by the output of the circuit 35. A horizontal synchronizing process mask circuit 36 is provided in relation to the counter 33. The circuit 36 produces a mask pulse MKP stopping a phase wave detecting circuit 37. This reduces the position shift of the vertical synchronizing pulse as well as the error.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and the present invention relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and the present invention relates to a synchronization signal regeneration circuit, and relates to a synchronization signal regeneration circuit, and the present invention relates to a synchronization signal regeneration circuit, and relates to a synchronization signal reproducing circuit that is capable of detecting vertical synchronization and output signals caused by a difference in horizontal phase detection output between even and odd fields of a television signal. This circuit prevents the phase shift of the pulse.

[Technical background of the invention]

FIG. 1 shows a synchronization pulse regeneration circuit used in a so-called countdown television receiver that synchronizes directly with a vertical synchronization signal.

11 is a voltage controlled oscillator that obtains an oscillation output with a frequency of 32 fu (horizontal frequency); 12 is a 1/16 frequency divider;
3 is a 1/2 frequency divider. The horizontal synchronizing pulse HP applied to the output terminal 14 has an oscillation output of 32 fH at l/16
Frequency divider 12 is obtained by frequency division by a 1/2 frequency divider 13.

On the other hand, there are 19 vertical synchronization signal input terminals, which are connected to the vertical synchronization detection circuit 15. This vertical synchronization detection circuit 15
A pulse is also applied to the reception from the vertical counter 17. The vertical counter 17 counts down the 2fH pulse and outputs the vertical synchronization i9 pulse vp to the output terminal 18, and also generates the reception/4' pulse.

Here, the vertical counter 17 is reset by the reset pulse R8P obtained from the reset pulse shaping circuit 16. The reset pulse shaping circuit 16 includes the vertical detection norm VDP and 2fH from the vertical synchronization detection circuit 15.
pulse is input. This reset pulse shaping circuit 1
6, as shown in FIG. 2, a vertical detection pulse VDP is applied to the data input terminal 16k, and a 2fm i4 pulse is applied to the clock input terminal. And vertical detection i
The reset pulse R8P is set to be output when the 2fH clock falls during the rising edge of the 4th pulse VDP.

For a certain period of time from the time when this reset pulse R8P rises, the vertical counter 17 is
Output P. Therefore, the rising edge of the vertical synchronization pulse vP is phase synchronized with the falling edge of the 2fn clock, and the pulse width is also constant and is an integral multiple of 2fy.

Here, the voltage controlled oscillator 11 is automatically controlled to obtain an oscillation output synchronized with the received horizontal synchronization signal. That is, the phase detection output of the composite synchronization signal CS and the sawtooth signal SW obtained from the flyback pulse is the phase detection circuit l! Given from 821. Resistance 22. capacitor 23
, 24 form a filter.

FIG. 3 specifically shows the entire phase detection circuit 21. By applying a composite synchronizing signal C8 sawtooth signal SAW to the pace of the transistor Q5 and the pace of the transistor Q3, a phase detection output is output to the left of the transistor Q4. Get all.

Transistors Q3-Q6 form a multiplier, transistors Q1. Q2, resistor Ftl, and R2 form the entire load circuit. Further, il is a constant current source, El and E2 are bias power supplies, resistors R3 and R4 are pace resistors, and vce is a power supply.

[Problems with background technology]

In the conventional horizontal AFC circuit described above, there is no problem during the horizontal synchronization signal period even during the composite synchronization signal period, but the equivalent t4
During the four pulses and the vertical synchronization signal period, the phase detection output changes, giving a total fluctuation to the oscillation frequency of the oscillator.

In particular, as can be seen from the entire operating signal waveform in Figure 4, the frequency control directions of the voltage controlled oscillator obtained at the vertical synchronization signal start part of the first field and the vertical synchronization signal start part of the next field are completely opposite. The direction will be In FIG. 4, C8 is a composite synchronization signal, period TI is an equivalent pulse period, and T2 is a vertical synchronization signal. Also, SAW is a sawtooth wave signal, P
DS indicates a phase detection signal, and P indicates all vertical synchronization pulses. In this way, if the phase detection output fluctuates at the start of the vertical synchronization signal of an even field and an odd field, and the direction of the fluctuation is completely opposite, the vertical synchronization pulse vp
The rising phase of , as shown by ta and tb, differs from field to field. When such a phenomenon occurs, the entire screen becomes jittery or incomplete interlacing occurs, which impairs the image quality.

[Purpose of the invention]

The present invention has been made in order to cope with the above-mentioned circumstances, and its entire purpose is to provide a synchronization signal regeneration circuit that can suppress the phase shift of the vertical synchronization pulse in synchronization signal reproduction using the countdown method.

[Summary of the invention]

In the present invention, the horizontal synchronization processing mask circuit 3
6, the phase detection circuit 37 basically stops operating, causing the mask pulse MKP 1, and all of the above objectives have been achieved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows an embodiment of the present invention, in which a signal 31 is input to a T frequency divider 32 for obtaining HP, and is also input to a vertical counter 33 for obtaining a vertical synchronizing pulse vP. The vertical counter 33 includes a flip-flop circuit FF (J
~FF9 and dirt circuits Gl and G2. 34 is a vertical synchronization detection circuit, and input terminal 3
A vertical synchronizing signal separated from the composite synchronizing signal is inputted via the vertical counter 4a, and a pulse is given to the input terminal 34b upon reception from the vertical counter 33. This vertical synchronization detection circuit 34 is composed of dart circuits 03 to Gll, and outputs a vertical synchronization detection pulse VDP' to an output terminal 34c.

The vertical synchronization detection pulse VDP is applied to the input terminal 35a of the reset pulse shaping circuit 35.

A 2ht pulse from the n frequency divider 31 is applied to the input terminal 35b of the reset pulse shaping circuit 35. Reset) No. 4 Rus molding circuit 35 is dirt circuit 01
2 to G21. And vertical synchronization detection A? A reset of a certain width at the first 2fH after the rise of Luss VDP and the fall of Luss R8P
The entire output is output and added to the reset terminal of the vertical counter 33. After receiving the reset pulse R8P, the vertical counter 33 outputs a constant width vertical synchronizing pulse vp'l to the output terminal 33a.

Here, a horizontal synchronization processing mask circuit 36 is connected to the vertical counter 33. The horizontal synchronization processing mask circuit 36 is
Flip circuit FF2 of vertical counter 33; FF
4 and dirt circuit G2, flip f 70 tube circuit FF9
input, and during the vertical synchronization signal period T2 and the equivalent pulse period TI before and after this, mask-tsu and rus-MKP'
fr occurs. (See FIG. 6) Consists of a vertical synchronization processing mask circuit 36Jd and dart circuits 022 to G25,
The output mask pulse MKP is applied to the operation stop control terminal 37h of the phase detection circuit 37.
8. A sawtooth wave signal SAW shaped like a flypack is input to the input terminal 37e, and a control signal SGN'e proportional to the phase difference of the re-input signal is input to the output terminal 3rd.
ffl force. The phase detection circuit 32 includes transistors Qll and Q whose emitters are commonly connected to a constant current source izz.
The composite synchronization signal C8 is applied to the pace of transistor Q13, and the mask pulse MKP is applied to the pace of transistor Q12. Also,
The bias power supply E11 is used to pace the transistor Qll.
is connected. Transistor Q12. The collector of QI3 is connected to the power supply vcc, and the collector of transistor Qll is connected to transistors Q14. Connected to the common emitter of Q15. Transistor Q14. Q15 pace is connected to bias power supply E1 via resistors R11 and R12, respectively.
2 and also to the pace of transistor QJ4,
The sawtooth signal SAW is provided. Transistors Qll to QJ5 constitute a multiplier, and transistor Q15
The collector of output terminal 37. d, and is also connected to the collector of transistor Q1B. Further, the collector of transistor Q14 is connected to transistor Q1.
7 and the pace of transistor Q16. Transistor Q16. Q11. Q18 forms the entire load circuit, the collector of the transistor Q16 is grounded, and the emitter is connected to the transistors Q17... through a resistor R13. It is connected to the pace of Q1B and further connected to the power supply vcc via a resistor R14. The emitters of the transistors Q 1,7 and QlB are connected to the resistor R15,
They are connected to the power supply vcc via R16, respectively.

One embodiment of the present invention is constructed as described above, and the relationship among the composite synchronization signal C8, vertical detection pulse VDP, vertical synchronization pulse vP, mask pulse MKP, and phase detection signal PDS is as shown in FIG. Become. In other words, in the case of this system, this period (
For example, during the 257th to 0th to 6th horizontal periods), the operation of the phase detection circuit 37 is stopped. Therefore, there is no possibility of outputting an erroneous detection signal whose phase is synchronized with the equivalent i4 pulse or the vertical synchronization signal, as in the conventional case. That is, conventionally, the phase detection output fluctuated in the opposite voltage direction between the even and odd fields during the equivalent pulse and vertical synchronization signal periods, but this system prevents such fluctuations. As a result, the rise of the vertical synchronization i4 pulse is
The phase is always constant and complete interlace operation can be achieved accurately.

The present invention is not limited to the above-mentioned embodiment, and the functions may be further enhanced by adding a vertical free oscillation detection circuit 40 as shown in FIG. The vertical free oscillation detection circuit 40 has a reset pulse R8P at the input terminal 40h.
A vertical synchronization signal is applied to the input terminal 40b, and a vertical synchronization detection pulse vP is applied to the input terminal 4θC. This detection circuit 40
is composed of dirt circuits 031 to G3B.

This vertical synchronization detection circuit 40 operates during periods when there is no vertical synchronization signal such as when switching channels.
This is a circuit that prevents P from being output and increases the horizontal synchronization pull-in speed.In other words, in the previous embodiment, the mask pulse MKP is output even when there is no vertical synchronization signal, such as when switching channels on a television receiver. are obtained, 257th to 288th,
The operation of the phase detection circuit 37 is stopped during the 0th to 6th horizontal scanning periods (0th being the rising edge of the vertical synchronization Noculus).

During this period, the horizontal pull-in speed of the horizontal automatic frequency control loose becomes slow. In such a case, so-called horizontal orientation occurs on the screen. Therefore, in the vertical free oscillation state, that is, when the vertical synchronization pulse vp is asynchronous with the vertical synchronization signal, it is better to turn off the mask and the las MKP. Therefore, when the vertical counter 33 is reset by the vertical synchronization signal, that is, when vertical synchronization is applied by the vertical synchronization signal, the presence of the reset pulse R8P in the vertical synchronization pulse vP period is used to In this state, there is no influence on the mask pulse MKP, and if the reset pulse R8P is output outside the vertical synchronization/f pulse vP period, this is considered to be a vertical free oscillation state. When in the vertical free oscillation state, a cancellation pulse of opposite polarity is obtained from the dart circuit 35 in synchronization with the mask pulse MKP. Therefore,
In the vertical free oscillation state, the phase detection circuit 37 operates without being stopped, and a horizontal pull-in operation can be quickly obtained.

〔Effect of the invention〕

As described above, the present invention provides an AFC signal in the vertical synchronizing signal and the equivalent pulse period in countdown type synchronous playback.
It is possible to provide a synchronization signal regeneration circuit that can suppress a shift in the rising and sand phases of a vertical synchronization pulse due to fluctuations in the output of a phase detection circuit in a loop.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the entire configuration of a conventional synchronization signal regeneration circuit, Fig. 2 is an explanatory diagram of the operation of the reset Noculus forming circuit shown in Fig. 1, and Fig. 3 is a circuit diagram showing the phase detection circuit shown in Fig. 1. , 4th
The figure is a power signal waveform diagram for each part of the synchronization signal regeneration circuit in Figure 1,
FIG. 5 is an explanatory diagram showing the entire configuration of one embodiment of the present invention, FIG. 6 is a signal waveform diagram shown to explain the invention in detail, and FIG. 7 is an explanatory diagram showing the entire configuration of another embodiment of the invention. It is a diagram. 3...1 frequency divider, 32...-frequency divider, 33...
Vertical 62 Direct counter, 34... Vertical synchronization detection circuit, 35...
Reset Noculus shaping circuit, 36... Horizontal synchronization processing mask circuit, 37... Phase detection circuit, 40. ...Vertical free oscillation detection circuit. Figure 1 Figure 2 No. 16 Figure 3

Claims (2)

[Claims] (1) A voltage controlled oscillator, a first frequency divider that divides the oscillation output of the voltage controlled oscillator, and a first frequency divider that further divides the output of the tenth frequency divider to generate horizontal synchronization noggles. 20 frequency divider and a vertical counter that divides the entire output frequency of the first frequency divider; A phase detection circuit is provided, into which a sawtooth wave signal obtained by converting the generated flyback pulse and a composite synchronization signal are input, and the phase detection output of both human power signals is applied to the control terminal of the voltage controlled oscillator through a filter. In a countdown type synchronization regeneration circuit, the count output of the vertical counter is used to increase the detection operation of the phase detection circuit during the vertical synchronization signal and equivalent pulse period of the composite synchronization signal. A synchronous reproducing circuit characterized in that it is equipped with all vertical synchronization processing mask means. (2) The vertical synchronization processing mask means includes the vertical synchronization processing masking means.
a vertical synchronization detection circuit that stops outputting the mask 4' pulse when a reset noculus for the vertical counter in the pulse generation means and a vertical synchronization signal separated from the composite synchronization signal are in an asynchronous state; A synchronizing signal reproducing circuit according to claim 1, further comprising: a synchronizing signal reproducing circuit according to claim 1.