JPS60751A - Manufacture of substrate for semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor integrated circuit.

In particular, the present invention relates to providing a manufacturing method that realizes a structure that increases the integration density of dielectrically isolated semiconductor integrated circuits.

In semiconductor integrated circuits, keeping the dimensions of each part to the necessary minimum and increasing the integration density is extremely important and the first effective means from the standpoint of improving the degree of integration, reducing costs, and improving performance. .

Recently, a wide range of studies have been started on high-voltage dielectric isolated semiconductor integrated circuits, in which an island-like single crystal semiconductor layer (hereinafter referred to as a high-voltage island) forms high-voltage elements and an island forms low-voltage elements. The thickness of the single-crystal semiconductor layer (hereinafter referred to as a low-pressure island) is made different. In other words, the depletion layer extension width is small.

The method of reducing the thickness of low-voltage islands, which are usually designed with shallow junction depths, is one of the concrete ways to improve the integration density of semiconductor integrated circuits.Compared to conventional high-voltage islands, As a manufacturing method for thinning a low pressure island, the method shown in FIG. 1 is known. That is, the first
As shown in Figure (a), the region corresponding to the low-pressure island of the single crystal semiconductor 1 is first removed by a depth D so that the bottom surface becomes flat, forming a depression. In this manner, a V-shaped groove is formed by alkaline anisotropic etching in a portion corresponding to the separation region of each high-pressure and low-pressure island. Next, as shown in FIG. 1(C), an insulating film 2t is formed on the main surface.
- and then a thick polycrystalline semiconductor layer 3 is formed thereon as shown in FIG. 1(d). Next, the single crystal semiconductor 1 is removed by polishing or the like from the back side to the tip of the V-shaped groove to form an island electrically isolated by an insulating film 2. There are the following manufacturing problems. That is, the V-shaped groove of the high pressure island (
Hereinafter, the V of the low pressure island and the first V-shaped m4 will be referred to as
In forming the V-shaped groove (hereinafter referred to as the second V-shaped groove 5), photolithography is performed, but the first problem is the difficulty in forming the 7-lithography 2-fee. That is, although it is not shown in FIG. 1(b), when performing selective anisotropic etching, a mask material (usually 5iQz
film) by photolithography, but since the mask material for the first V-shaped groove 4 and the mask material for the second V-shaped groove 5 are on different planes, it is difficult to decide whether to perform normal photolithography twice or not. There is no choice but to significantly sacrifice the processing of the mask material. In the latter case, the depth D in Figure 1(a) is 30
It is almost impossible because it is usually on the order of μm.

Roughly speaking, the second problem occurs when the first V-groove 4 and the second V-groove 5 are formed by anisotropic etching at the same time. The difference is that the amount of machining and removal of sheeting differs significantly. for that,
This results in over-etching for the second V-shaped groove 5. As a result, the shape of the corners of the low-pressure island (which is usually seven times smaller in thickness than the high-pressure island) is compromised. As a countermeasure, there is a method of forming the first V-shaped groove 1114 and the second V-shaped groove 5 separately, but this increases the number of steps.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit substrate in which photolithography is easy and an island region of a predetermined shape can be easily obtained.

According to the present invention, grooves for high voltage and low voltage are formed in a semiconductor substrate by anisotropic etching, and a mask member is selectively formed and anisotropically etched to continue part of the groove for high voltage and the groove for low breakdown voltage. A method for manufacturing a semiconductor integrated circuit substrate is obtained.

Hereinafter, the present invention will be explained in more detail based on Examples.

FIG. 2 is a sectional view showing an embodiment of a method for manufacturing a dielectrically isolated semiconductor integrated circuit according to the present invention.

In FIG. 2 (ta), an insulating film 6 such as an 8i02 film is formed on the surface of an N-type single crystal semiconductor 10 having a (100) plane, and a portion corresponding to the first V-shaped groove 4 is formed by photolithography.

In addition, an opening is provided in a portion corresponding to the low-voltage element formation region to indicate a friendly state. Here, the width of the opening on the side of the first V-shaped groove 4 is determined by calculating backward from the desired depth of the first V-shaped groove 4. The thickness of the insulating film 6 is determined by calculating backward from the film thickness required as a mask material for the next anisotropic etching.

Figure 2(b) shows anisotropic eratin blur using an alkaline etching solution. After removing it in a U-shape, create a new B i
A state in which an insulating film 7 such as a Qz film is formed is shown.

Here, the amount removed when removing in a U-shape is shown in Figure 1 (a).
This is the same amount as the depth D in the figure. Further, the insulating film 7 formed here has a thickness determined by back calculation from the film thickness required as a mask material for anisotropic etching to be performed later. Typically it is from a few thousand angstroms to a few micrometers (μm).

FIG. 2C shows a state in which the bottom surface of the U-shaped groove corresponding to the first V-shaped groove 4 and the insulating film 7 corresponding to the second V-shaped groove 5 have been removed by photolithography.

In removing the insulating film 7t, not only the bottom part of the U-shaped groove but also a part of the side part is removed. The crystal plane exposed on the side surface is the (111) plane, and when primary anisotropic etching is performed, the U-shaped groove becomes a V-shaped groove, even though the crystal is exposed on the side surface. is formed. Figure 2 (
d) shows that new 5i is formed on the main surface after the anisotropic etching.
2 shows a state in which an insulating film 2 such as a 02 film is formed and covered. FIG. 2(e) shows a state in which a thick polycrystalline semiconductor layer 3 of several hundred micrometers is formed on the insulating film 2. As shown in FIG. (Fig. 2) is removed from the back side of the single crystal semiconductor 1 to the tips of the first and second V-shaped grooves by a method such as polishing, and the high voltage and low voltage This shows a state in which an island is formed. Thereafter, high-voltage elements are formed on the high-voltage islands, and low-voltage elements are formed on the low-voltage islands, and predetermined elements are connected using scrap metal wiring to construct a desired circuit and complete manufacturing.

The details of the manufacturing method according to one embodiment of the present invention have been described above. It is clear that the manufacturing method according to the invention overcomes the problems of conventional manufacturing methods. That is, although anisotropic etching is performed twice, unlike the conventional method, in the manufacturing method according to the present invention, the amount of etching removed in the depth direction is the same for both the first V-groove 4 and the second V-groove 5. be. That is, the manufacturing method according to the present invention provides a solution to the problem of over-etching on the second V-groove 5 side, especially the collapse of the corners of the island, which was a problem with the conventional manufacturing method.

In addition, the bottom surface of the U-shaped groove of the first V-shaped groove 4 and the second V-shaped groove 5
It is clear that the opening is on the same plane as the opening in the insulating film γ in the step C1 shown in FIG. 1 (b).
) It becomes possible to save the margin shown in the figure 1, and the area efficiency can be improved accordingly.

Finally, the manufacturing method according to the present invention is not limited to the above-mentioned embodiment, but before forming the insulating film 2 in the step shown in FIG. It is also possible to improve the characteristics of the element by diffusing small N-type impurities and forming a high impurity concentration layer on the entire bottom side of the island.

In addition, the manufacturing method according to the present invention is similar to the above embodiment, in which N
It is not limited to single crystal semiconductors.

It is clear from the gist of the present invention that the present invention can also be applied to a PN type single crystal semiconductor.

[Brief explanation of the drawing]

1(a) to 1(e) are cross-sectional views showing a conventional method for manufacturing a dielectrically separated semiconductor integrated circuit in the order of steps, and FIG. 2(a)
) to ff) are cross-sectional views showing a method for manufacturing a dielectrically isolated semiconductor integrated circuit and an integrated circuit according to an embodiment of the present invention in the order of steps. l... Single crystal semiconductor, 2... Insulator,
3... Polycrystalline semiconductor layer, 4... 1st V
'f-groove, 5...2nd V-groove% 6...
・Insulating film, 7...Insulating film 1M bud 1] Dye 2 times, 2 times

Claims (1)

[Claims] In a method for manufacturing a dielectrically isolated semiconductor integrated circuit, a predetermined isolation region of a region where a high breakdown voltage element of a single crystal semiconductor is formed and a whole or part of a region where a low breakdown voltage element is formed are different. A step of selectively removing a U-shape by a directional etching method, followed by a step of forming and covering the main surface of the single crystal semiconductor with a first insulating film, and a step of removing a predetermined region in which a high breakdown voltage element is to be formed. A bottom portion of the U-shaped groove corresponding to the separation region, and. removing the first insulating film from a predetermined isolation region on the bottom of the U-shaped groove corresponding to a region where a low breakdown voltage element is to be formed, and performing anisotropic etching in this state to form a single-shaped groove; a step of forming and covering the main surface of the single crystal semiconductor with a second insulating film, a step of forming a thick polycrystalline semiconductor layer on the second insulating film, and a step of forming the tip of the single-shaped groove from the back side. A method for manufacturing a substrate for a semiconductor integrated circuit, comprising the steps of: removing the single crystal semiconductor up to a certain point, and processing the single crystal semiconductor into an island shape separated by an insulating film.