JPS6076096A - Method and device for write of ep-rom - Google Patents

Abstract

PURPOSE:To ensure programming with high efficiency by performing high-speed programming simultaneously with plural EP-ROMs and replacing successively these EP-ROMs with which the correct data writing is through with new ones respectively and executing continuously the programming. CONSTITUTION:A control part 1 includes a keyboard 1A which indicates a writing operation from outside, a display device 1B for data to be written, data read out of an EP-ROM, the operation state, etc., and a data buffer 1C which stores the data to be written to the EP-ROM. A display device 3 is provided to a writing part 2 to display an end. At the part 1 the program voltage is applied to the EP-ROM and data are transferred together with the control given so that the program pulses having comparatively small width are applied continuously. In such a way, the EP-ROMs with which the writing is through are displayed regardless of the type of the program especially when the data of the same contents are written to many EP-ROMs. Thus these displayed EP-ROMs are replaced with new ones. This improves the writing efficiency.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an erasable programmable ROM (hereinafter referred to as EP-
EP-R that can effectively write data to ROM (referred to as ROM)
The present invention relates to an OM writing method and device.

[Technical background of the invention]

Conventionally, EPs with a relatively small capacity, for example, 8 bytes,
- In ROM, writing is performed by applying a narrow program pulse to all addresses n times, but in this case, the total pulse width of the program pulses applied to a specific address is is null to a constant value.

On the other hand, an EP with a large capacity such as 64 bytes or more
- Writing to ROM can be performed using a method called high-speed programming. In this high-speed programming, a program pulse with a narrow pulse width is applied to one address, and then data at that address is read out, and this process is repeated until correct writing is performed. If the writing is correct, an additional program pulse is then applied. Then, the address is updated and writing is performed again using the method described above.

[Problems with background technology]

When the above-mentioned high-speed programming is performed simultaneously on M EP-ROMs, the number of program pulses applied until correct data is written is not equal.

Especially EPs that require a significantly large number of program pulses.
- With ROM, the time required to complete the program is dominated by the difficult EP-ROM of this program, thereby increasing the overall program time. Also, in order to eliminate this problem, multiple E
It becomes necessary to specify addresses separately and independently for each P-ROM, and the configuration of the embedded device becomes complicated, and one device programs many EP-ROMs at the same time, increasing the cost of the device. The advantage of reducing this will also be lost.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and when performing high-speed programming of a large number of EP-ROMs with one writing device, it shortens the time required for the entire program, thereby making it possible to efficiently program C. EP-ROM that can perform
[Summary of the Invention] That is, the present invention aims to provide a method and apparatus for simultaneously programming a large number of
EI'-
When a ROM occurs, it is displayed, the program is temporarily stopped, the EP-ROM is removed, and a new EP-RQM is installed here and the program is restarted. It is.

[Embodiments of the invention]

The method of the present invention will be explained in detail below with reference to the block diagram shown in FIG. In the figure, 1 is a control section, and 2 is a writing section. The control unit 1 includes a keyboard 7A for externally instructing write operations, a CRT for displaying data to be written, data read from the EP-ROM, operation status, etc.
A data buffer IC is provided for storing data to be written to an indicator IB such as an LED and an EP-ROM. The writing section 2 is provided with a plurality of sockets 2A, 2B, . Then, the control unit 1 connects the socket 2 of the writing unit 2 to 2B...
A program voltage is applied to the EP-ROM installed in the EP-ROM, data is transferred, and program pulses having a relatively narrow pulse width are repeatedly applied.

FIG. 2 is a flowchart showing a write operation (program) to the EP-ROM.

In other words, if you "start" with 8TEP1, you will get 5TEP!
``Execute execution counter X=0-J.''

Here, the execution counter is a counter that sets the number of times the entire program routine is tried. For example, the limit is N times, and if the number is more than N times, the EP-ROM is determined to be a permanently defective product. And 5TEP? Address counter AD
Set the initial address △△△△ to . And the next 8TE
EP-ROM specified by address counter AD in P4
A judgment routine that reads the data and compares it with the written data [Did the read data match the written data? ”
Do the following. If the judgment result of this 8TEP4 is "NO", that is, the data does not match, "execute the program" in the next 8TEP5, and if rYE8J, that is, the data match, "address increment" is executed in 5TEP6, and then 5TEP4 is executed again. Let's do it. In addition, the above 5TE
In the program execution of P5, only one program pulse with a relatively narrow pulse width ty is applied in order to perform high-speed programming.

Then, in the next step 5TEP7, it is determined whether the address counter has reached the end address. If this determination result does not reach r N OJ, that is, the end address, "address increment" is executed in 5TEP6, and the process returns to 5TEP4.

Further, if the determination result of 5TEP7 is 1-YESJ, 1 execution counter X=X+IJ is executed in the next 5TEP&.

Then, in step 8TEP9, it is determined whether correct data has been written to all addresses.

If this judgment result is "YES", "execution of additional program" is performed at 8TEP10.0 This additional program is executed until, for example, the data in the EP-ROM matches the write data (=program pulses equal to the number of applied program pulses). is further applied. After this, further 5TEPJ J is used to determine "confirm data of all addresses", and if this result is rYEsJ, "writing is complete".
The completion of writing is displayed on a display (not shown) corresponding to the EP-ROM.

If the determination result of 5TEP9 is "NO", that is, the data has not been written correctly, 5TEPI2 determines "Is the execution counter N?". This judgment result is Y
If it is ES, it is considered to be permanently defective. If still no, 5
Return to TOPJ, set the address counter AD, and run the program again. Note that even if the determination result of 5TEPII is "NO", that is, data at all addresses are not correctly written after the execution of the additional program, it is considered to be a permanent failure.

In this way, especially when writing the same data to a large number of EP-ROMs, the EP-ROM that has been written will be displayed regardless of the difficulty of the program, so that new EP-ROMs can be created. By replacing it with a ROM, writing can be performed efficiently.

Note that the present invention is not limited to the above embodiments; for example, the additional program may be defined by pulse width rather than the number of pulses, or pulses with narrow pulse widths may be defined at once without dividing into multiple pulses. Alternatively, the voltage may be applied.

[Results of the invention]

As described above, according to the present invention, high-speed programming can be performed efficiently, and the EP-1 is particularly suitable for applications in which data with the same content is stored in a large number of EP-ROMs. A method and apparatus for writing OM can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the apparatus of the present invention, and FIG. 2 is a flow chart showing the method of the present invention. 1... Control section, 2... Writing section, 3... Display device. Applicant's agent Patent attorney Takehiko Suzue Commissioner of the Patent Office Kazuo Wakasugi 1. Indication of the case Japanese Patent Application No. 58-182725 2, name of the invention EP-ROM writing method and device 3, relation to the supplementary case Patent applicant αm Tokyo Shiba; 1n Electric Co., Ltd. 5, voluntary supplementary

Claims (3)

[Claims] (1) After specifying the address and data to the EP-ROM, apply a program pulse with a constant pulse width, and then update the address and apply the program pulse until all data has been written. It is characterized in that a repeated high-speed program is simultaneously executed on multiple EP-ROMs, and the EP-ROMs in which correct data has been written are sequentially replaced with new EP-ROMs to continue executing the program. How to write to EP-ROM. (2) A high-speed program that specifies the address and data to the EP-ROM, applies a program pulse with a constant pulse width, and then repeats the update of Natres and the application of the program pulse until all data has been written. What is claimed is: 1. An EP-ROM writing device for simultaneously performing data writing on a plurality of EP-ROMs, characterized in that an indicator is provided for each of the plurality of IP-ROMs to indicate that all data writing has been completed. (3) In what is stated in claim 2, EP
- An EP-ROM writing device characterized in that after the data stored in the ROM and the data to be written match, a predetermined additional program is executed to complete the writing.