JPS6076168A - Insulated gate semiconductor device manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a vertical channel type ff1 layer type insulated gate type semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.

The present invention provides at least three gate electrodes for this IGF.
The gate electrode is provided on the gate insulator around the side of the semiconductor stacked in layers, and the upper end of this gate electrode is formed without extending above the stacked semiconductors, and the purpose is to operate at a higher frequency. .

The purpose of this invention is to provide highly integrated circuit elements such as inverters by fabricating two IGFs using the two side peripheries of a 3M 1jf4 layered semiconductor.

The present invention relates to a method for manufacturing a composite semiconductor device having a capacitor connected to the source or drain of a stacked IGF on a substrate.

The present invention is characterized in that such a composite semiconductor device is provided on a substrate in a matrix structure to produce a device on a liquid crystal display type display. - When manufacturing a flat solid state display device, there are known liquid crystal or electrochromic display devices in which a pair of electrodes is provided in parallel light-transmitting substrates, such as glass or plastic plates, and liquid crystal is injected between the electrodes. There is. However, in this case, the number of picture elements in this display section is 20~
The limit is up to 200 pixels, and if it is larger than that, the number of terminals taken out from the display section would be equal to the number of picture elements, so it could not be put to practical use at all.

Therefore, in order to make this display section into a plurality of picture elements, configure them into a matrix, and turn any picture element into an on or off state by controlling it with a logic circuit of a decoder and driver provided around the picture element, it is necessary to It was necessary to manufacture the IGF, inverter, resistor, etc. corresponding to the picture element using the same process and the same structure. A control signal is then given to this IGF to turn on or off the corresponding picture element.

This liquid crystal display or electrochromic display element uses a capacitor (hereinafter referred to as C) as a 1111 circuit.
It can be shown in For this reason, the first
Shown in Figure (A).

In Figure 1 (Δ), one address of matrix (40) is one IG, F (10) and one c (31).
One picture element is constructed by this. Add this to the line (51
), < 52 ) are connected to the L'soto line, and external forces and gates are connected to provide columns (41) and (42X words).

Then, for example, (51) and (41) are set to "1", and (5
When 2) and (42) are set to "0", IGF (10) is turned on and other IGFs such as IGF (10') are turned off. Then, by selecting only the address (2, 1) and turning it on, it is possible to electrically turn on the display section indicating the number of nights, such as C (31).

The present invention is characterized in that the matrix-structured IGF is made symmetrical, thereby reducing the area required for IGF wiring other than the display area. Furthermore, by using a vertical channel type, carrier mobility is low even when using a non-single crystal semiconductor of 5ixC1-x (Q<x<1), which is silicon whose main component is silicon doped with hydrogen or fluorine. It has its drawbacks. For this reason, the film thickness of the second semiconductor is set to 1 μm.
or shorter channel length. the result,
It was possible to have a cutoff frequency higher than IOMH2.

As shown in FIGS. 1 <B), <c), and <D>, the present invention allows a decoder and a driver to be configured on the same substrate, so that other insulated gate type semiconductor devices (10) and an inverter (60) can be used. , and a resistor (70) on the same substrate.

Thus, by combining the present invention based on its design specifications, it was possible to create a solid-state display device for flat televisions that can replace cathode ray tubes.

FIG. 2 shows a longitudinal cross-sectional view of the stacked IGF of the present invention and its manufacturing process. This drawing shows a manufacturing example in which one IGF is manufactured, but the manufacturing example in which multiple IGFs are manufactured on the same substrate is exactly the same.

In the drawings, a first conductive film (2) (hereinafter referred to as FBI) was provided as a lower electrode or lead on an insulating substrate, such as a quartz glass or borosilicate glass substrate.

In this embodiment, a transparent conductive film containing tin oxide as a main component is formed to a thickness of 0.2 μm. Selective etching ■ was applied to this. Furthermore, a first non-single crystal semiconductor (2) (hereinafter simply referred to as 31) having a P or N type conductivity is formed on this upper surface.
1000-3000 people, second intrinsic or N or P
type semiconductor (4) (hereinafter simply referred to as 52><0.3 to 3
μ), and a third semiconductor (5) (hereinafter simply referred to as S3) (0.1 to 0.5 μ) having the same conductivity type as the first semiconductor was laminated. Through this lamination, NP-N, NIN,
It had a PN-I', PIF junction. This N, P
Let Nga or P”P be N+NINN”, P”
It was effective to lower the contact resistance with the electrode by using ``PIPP''.

These Sl, S2. The S3 semiconductor is prepared using silane (7) on the substrate using the C1-discharge method (PCVII method, photo-CVO method,
LT CV [] method (IIOMO (also called: VD method))
Amorphous or semi-amorphous (amorphous) or semi-amorphous (
A non-single crystal silicon semiconductor with a semiamorphous or polycrystalline structure is used. The present invention focuses on amorphous or semi-amorphous semiconductors (hereinafter referred to as SAS and tI).

Furthermore, in FIG. 2(B), S3 is removed by selective etching using a mask .
1 is removed and the remaining semiconductors S1 to S3 are
1 were formed into the same shape. All using the same mask, plasma vapor phase etching, for example, using IIF gas, 0.1 to 0.5 to
The etch rate was set to rr30W and an etching rate of 500 people/min.

In order to make the insulating film formed later on this S3 even thicker, LP CVD method (low pressure vapor phase method), PC
A G silicon oxide film having a thickness of 0.3 to 1 μm may be formed in advance by a VD method or a photo-CVD method. In the case of the PCVD method, the reaction between NLO and S1111 was carried out at 250°C. Also, add MoJ of 0.2 to 0.5 on this S3.
It was effective to improve the conductivity of S3 by forming 5XOL with a thickness of 0.3 to 1 μ on top of the μ and forming a matrix.

After this, these semiconductors Sl (13 in 52 (14),
Photo-CVD silicon nitride film (16) covering S3 (15)
The film was produced by a gas phase reaction of silane (disilane may also be used) and ammonia under the conditions of 250° C. and 2 Lorr using a mercury excitation method, and the thickness was 300 to 2,000.

This insulating film may be activated by electromagnetic energy at a frequency of 13.56MI+2 to 2.45Gl+2 and immersed in an atmosphere of oxygen or a mixed gas of oxygen and hydrogen at 100 to 400°C to form silicon in an in-phase-gas phase reaction. .

Alternatively, a multilayer structure may be obtained by forming silicon nitride or phosphorus glass by IIcVD method.

Then, around the 32 (14) side, the gate insulator (16
) as this! (The edges are formed and the surfaces of SL and S3 can be formed as an isolation film).

In FIG. 2(B), an electrode hole is further formed using a third mask (2), and then a second conductive film is formed to a thickness of 0.3 to 1 μm covering the silicon nitride film on this Sl, 52.53. It was formed.

This conductive film (17) is ITO (rlI indium)
Transparent conductive film such as hhLIMO3IZ l dizziness,
W, Ti.

A heat-resistant conductive film such as Mo may also be used. Here, a silicon semiconductor heavily doped with P or N type impurities is used as a PCV.
Made using the o method. That is, a microcrystalline (grain size 50 to 300) non-single crystal semiconductor having a thickness of 0.3 μm and having 1% phosphorus added thereto was fabricated by the PCVO method.

After that, a resist (18) was formed on this upper surface.

Further, as shown in FIG. 2(C), anisotropic etching was performed in the vertical direction using a photolithography technique of ff14. That is, for example, CF, CIL, CF, +O
L.

A reactive gas such as 11F was turned into plasma, and the plasma was applied vertically from above the substrate as shown by the arrow (28). Then, the conductor (17) has a thickness of 0.3 on the plane.
μ), this coating is removed, but on the side surfaces Sl, S2. 2 of the sum of the thickness of S3 and the thickness of the coating
．． It has 2-3μ in the vertical direction. Therefore, if anisotropic etching is performed in the vertical direction as shown in the drawing, the broken line (3B
), (,3B'), these conductors are masked (18
) could be left in other areas as well. As a result, S
l, S2. It was possible to selectively provide the gay 1 electrode only around the S3 side. Furthermore, this gate electrode does not exist above the third semiconductor, and as a result, the parasitic capacitance between the third semiconductor and the gate electrode can be made substantially equal to zero.

Thus, FIG. 2(C) was obtained.

Furthermore, the part marked ■ in <V> in Figure 2 was removed using a plasma etching method, and the (20) and <2
Only 09 was formed as a gay 1-electrode.

The plan view of FIG. 2(C) is shown as FIG. 2(D). The numbers correspond to each other.・Figure 2 <c>, (
It is clear in D) that the IGF (10) has two channels (9) and (9'), a source or drain (13), a drain or source (15), and a gate ( 20>, <20'). The lead of S3 is (
According to (21), the lead of Sl is provided according to (22). That is, in the drawing, two IGFs can be provided as a pair. This means that the 32 semiconductors between the channels of two IGFs are non-single crystal, and if 32 have a diameter of 10μ, several M
It has a resistance of Ω and can be configured substantially independently. The present invention utilizes the unique characteristics of this amorphous semiconductor. This structure made it compatible with crystalline semiconductors (it was possible to have a different structure).

The semiconductor of the present invention uses a non-single crystal semiconductor containing amorphous silicon, hydrogen is used to neutralize the dangling bonds in the semiconductor, and the substrate, semiconductor, and electrode leads are made of different materials, and the heat generated by them In order to reduce stress due to expansion, all treatments were preferably carried out at 600°C or lower, preferably 300°C or lower.

In addition, the gate electrodes (20>, (20') are connected to Sl (13)
, S2 (14-input S3) It is also possible to provide a non-volatile memory by using a semiconductor similar to S3 (15) and providing it as an electrically floating structure, and using the second gate as a control gate with an insulating film interposed on the upper surface thereof.

Thus, the source or drain is S1 (i3), S2 (14) with channel forming region (9), <9')
, a drain or a source is formed by 33 (15), and a Dito insulator (16) is formed on the side surface of the channel forming region.
We were able to create a stacked IGF (10) with Dito electrodes (20) and (20') provided on its outer surface.

In this invention, the channel length is determined by the thickness of s2 (14), generally 0.1 to 3μ, here 0.5μ. This is because the mobility of a non-small crystal semiconductor is different from that of a single crystal, and the channel length can be shortened to improve the frequency characteristics of an IGF.
There is something in U.

Furthermore, in the IGF of the present invention, since the electron mobility is 5 to 100 times higher than that of holes, it was preferable to use an N-channel type.

Boron impurity was added to S2 during film formation (0,1~1
011) It was effective to control the threshold voltage by adding it as an intrinsic or P or N semiconductor.

It was possible to obtain an operating frequency of 15.5M1lz with <L/teVbo-5V+% (, = 5V).

FIG. 3 shows a longitudinal sectional view of a portion of the display panel of FIG. 1(A) using the IGF of the present invention shown in FIG.

Figure 3 (A) shows the IGF' (10), (10
'), which shows the upper electrode of the capacitor (X32 provided on the lower side in FIG. 3). In the drawing,
A-A" and B-B" vertical cross-sectional views of the plan view of (A) are shown in (B).
) and (C).

In the drawing, Sl (13), S2 (14 in 53
For the semiconductor (15), there are two lower electrodes (12>, (
1-2'> is provided. The upper electrode (19)
A lead (51) is provided in the direction. The gate electrode (20') has two IGF regions (Fig. 3(A)
) except for the region (10>, (10')) surrounded by dashed lines, leads (41).

(42) in the Y direction. Lower electrode (12).

(12'> further extends to one electrode of the capacitor (
32), (32'). Thus, in the X direction, Y
It was possible to have a matrix configuration in the direction and an lTr/donation element structure. Furthermore, the areas (71) and <71') were filled with a display material, such as a liquid crystal, and the area (71) was controlled by turning on and off the IGFs (10) and (10'>).

In FIG. 3, it is effective to further cover the leads (51) with an insulating film.

Furthermore, as is clear from FIG. 3, the area required for the IGF of this display is less than 1% of the total area. The display area is 91% and the lead area is 8%. This means that the pair I
In addition to using GF, the required area on the substrate can be reduced because IGF has a short channel length. Another advantage is that the accuracy of photolithography does not limit the upper limit of the operating frequency.

An outline of the operation in FIG. 3 is shown corresponding to FIG. 1(A). In the N-channel IGF, all these IGFs are normally off, so the leads in the X direction (41>,
(42), the Y-direction lead (51), <52) could have a ``1'' when voltage was applied to both sides, and a ``0'' when only one side was applied or no voltage was applied. .

Furthermore, in order to operate these picture elements at high frequencies, IGI
? The frequency characteristics of the present invention (7) are extremely important.
At IGF voltage = 5V and V voltage = 5V, it was possible to have a power cut-off frequency of 10 MIIZ or more <14.5 MIIZ XN channel IGF >. VTh=0.
It became possible to set the voltage to 2 to 2 V by controlling the concentration of impurities added to S2.

The IGF of the present invention will be described below with respect to the peripheral decoder, the resistors necessary for the driver, and the inverter.

FIG. 4 shows a longitudinal cross-sectional view of the inverter (60) of FIG. 1.

In FIGS. 4(A) and 4(B), the IGF numbers correspond to those in FIG. 2. The driver (61) is on the left
GF, and the right IGF was used for loading.

In drawing (A), the load dito electrode (20) and V (65
) and the continuous enhancement type, also drawing (B)
shows a depression type IGF in which the output (62) and the gate electrode (20) are connected.

Furthermore, the output of this inverter (60) consists of (62), which connects the two IGFs (61), <64) on this substrate to the same semiconductor block (13) without separating them from each other.

The feature is that (14) and (15) are provided in combination.

This impark in Fig. 4(A) connects the upper electrode to two FEs.
T was independent (19), <19'). When it is removed, one IGF (6480-de) is connected to the electrode (19).
.

drain (15), channel (9), source (13),
Electrode (12), i.e. output (62) and electrode (2) of the other IGF (driver), drain (13 channel (9')
), source (15'), and electrode (66). As a result, two IGFs are combined into one 51~
It was possible to integrate it with the s3 block to form an inverter.

Moreover, FIG. 4(B) shows the lower electrode divided into two parts. i.e. for one IGF load (64) (65), lower electrode (12 drain (13), channel (9), source (5), electrode (62) i.e. output (62), other IGF
Drain (15), channel (9'), source (13>, electrode (12'), νs5 at F (driver X61)
(66), and the input (63) is connected to the gate electrode (20
') pulled out the output (02') from S3.

The resistor (70) in FIG. 1 is determined by the resistivity of the bulk component of 52, independent of the voltage applied to the dito in FIGS. 2(D), <E) and FIG. 3(D). That is, it is determined by the resistivity of the bulk component of 82, regardless of the voltage applied to the gate electrode. In other words, in a state where no gate electrode is provided, Sl, S2. It is sufficient to stack S3. Further, this resistance value may be determined according to design specifications based on the resistivity of S2, its thickness, and the area occupied on the substrate.

As described above, the present invention is a vertical channel, and since the gate electrode uses a vertical anisotropic etching method, the same material as the gate electrode can be removed above S3 without using a mask. It has the great advantage of being able to reduce the parasitic capacitance between the electrode and S3. Two IGFs can be made simultaneously in pairs. It is sufficient to manufacture masks five times, and we have achieved many advantages such as not requiring mask precision, in addition to the fact that the channel length can be extremely short to 0.2 to 1 μm.

The display of FIG. 3 in accordance with the present invention has one electrode (3
2) determines the size of one picture element. In Curiculeik and the like, it has a size of 0.1 to 5 mm or a rectangular shape.

However, in the scanning type system as shown in Figure 1, 1 to 50
1000 x as a matrix-like picture element of 0'μ0
It was set to 1000. A liquid crystal display section (31) was provided on this substrate as another electrode of the capacitor. That is, the other electrode is a glass plate having a grounded transparent electrode such as ITO, and this glass plate and the substrate of FIG.
For example, a nematic type liquid crystal was injected into the gap with a gap of mm.

Further, this display may be displayed in color.

Furthermore, for example, these picture elements may be stacked in triplicate. Then, the three elements of red, green, and yellow should be arranged alternately -u.

Therefore, it was possible to control the breakdown voltage to 20 to 30V, for example, 1V±0.2V in the range of -4 to 4V. Furthermore, since the frequency characteristic is a microchannel with a channel length of 0.1 to 1 .mu., it was possible to obtain 10 MIIz or more, which is 50 times that of conventional non-single-crystal horizontal insulated-gay 1-type semiconductor devices.

In addition, reverse leakage is caused by Sl or S as shown in Figure 1.
By setting 3 to 5ixC1-) < (Q < x < 1, for example x = 0.2), impurities of this SL S3 are less likely to flow into 32, and this N-1
The leakage of the junction or P-1 junction was less than 10 n^/cIa even when IOV was applied in the opposite direction. This is 2 to 3 orders of magnitude lower than the reverse leakage of single crystals, which is preferable because physical properties specific to non-single crystal semiconductors are actively utilized.

Furthermore, if silicon carbide is made by adding, for example, 10 to 30 mol% of carbon to Sl, the structure shown in FIG.
/10' times less leakage. Naturally, this low leakage is extremely effective when implementing the matrix structure of FIG.

Furthermore, in operation at high temperatures, the metal of the electrode easily mixes into the non-single crystal 31, S3 and causes defects, so the side close to this electrode is
For example, X=0.2). As a result, 10 at 150°C
Although the device was operated for 1,000 hours, no malfunction was found even after evaluating 1,000 devices. This is an extremely high improvement in reliability considering that if 31 or S3 were formed of only amorphous silicon in close contact with this electrode, it would not withstand 150° C. for 10 hours.

Furthermore, because of such a stacked IGF, it has become possible to fabricate a plurality of IGFs, resistors, and capacitors on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past. This made it possible to develop it into liquid crystal displays.

The non-single crystal semiconductor in the present invention is silicon or silicon carbide (
SixC1-xO<x<1), and silicon oxide or silicon nitride was used as the insulator. However, as a semiconductor, In
m -v compound semiconductors such as +'+BP and GaAs may also be used.

[Brief explanation of the drawing]

FIG. 1 shows a matrix-structured circuit having an insulated gate semiconductor device, an inverter, a resistor, a capacitor, or an insulated gate semiconductor device and a capacitor as picture elements according to the present invention. FIG. 2 is a longitudinal cross-sectional view showing the process of manufacturing a stacked insulated gate type semiconductor device of the present invention. FIG. 3 is a vertical cross-sectional view of a composite semiconductor showing a flat display in which the stacked insulated gay 1-type semiconductor device of the present invention, a capacitor, and a display section are integrated. FIG. 4 shows the impark structure of the insulated gate semiconductor device of the present invention. Patent applicant Semiconductor Energy Research Institute Co., Ltd.

Claims (1)

[Claims] 1. A first non-single crystal semiconductor, a second non-single crystal semiconductor on the substrate or a first conductor on the substrate, and a semiconductor of the same conductivity type as the first semiconductor on the semiconductor. a step of stacking a third non-single crystal semiconductor; a step of forming the first, second and third semiconductors into substantially the same predetermined pattern shape; and a step of forming an insulator on the surface of the semiconductor. and forming a conductor or semiconductor that forms a Gefit electrode adjacent to the insulator on the side of the second semiconductor without the upper end of the gate electrode remaining on the third semiconductor. 1. A method for manufacturing an insulated gate semiconductor device, comprising: 2. In claim 1, the conductor or semiconductor constituting the gate is vertically anisotropically etched from above to form the gate without leaving the upper end of the gate electrode above the third semiconductor. A method for manufacturing an insulated gate type semiconductor device, characterized in that the device is formed adjacent to an insulator.