JPS607697A - Complementary semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify a clock input signal by connecting N channel FETs and P channel FETs alternately between resistors as a transmission gate. CONSTITUTION:The N channel FETs 10, 12 and the P channel FETs 11 are alternately connected between register circuits 31-3n as transmission gates respectively. The register circuits 31-3n are coupled by passage control transistors (TRs) such as the N channel FET10, P channel FET11 and N channel FET12 in series. The gates of the passage control type TRs are connected to clock input terminals 7 and the odd number-th passage control type TR is formed by an N channel FET and the even number-th passage control type TR is formed by a P channel FET respectively. Since the C-MOS shift register is formed as shown above, a clock input signal can be simplified.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary semiconductor integrated circuit using complementary MO8 elements, and particularly to a complementary semiconductor integrated circuit that can unify clock input signals. It is related to.

[Prior art]

An example of a conventional C-MOS shift register circuit is shown in FIGS. 1 and 2. In the figures, (1) is a data input terminal to which a data input signal is applied, and (2) is a data output terminal from which a data output signal is obtained. This is the data output terminal.

The circuit shown in FIG. 1 is a memory circuit element (hereinafter referred to as a register circuit) (31), (3z)
...(3n) is a fourth conductivity type MO8) transistor (hereinafter abbreviated as NchFET) (41, (!51,
(connected in series via 61..., and its NchFET
The clock signal φ and its inverted signal φ applied to the clock input terminals +71 and (8) connected to the gates are alternately input to each of the gates 47 to 61.

Figure 2 shows an NchFET instead of the NCllFET in Figure 1.
ET and the second conductivity type MO8+- transistor (hereinafter, Pc
hF, ET) are connected to each other, and clock signals φ and 2, which are inverted to each other, are input to the gate input of the NchFET and the gate input of the PchFET, respectively.

The operation of the C-MOS shift register circuit configured in this way will be explained using FIG. 1. First, the clock signal φ
is higher than the threshold voltage of NchFffT (hereinafter referred to as H
When the NchFET (J) is turned on, the input signal from the data input terminal (1) is transferred to the first register circuit (31). will be introduced in

At this time, since the inverted signal 7 of the clock signal φ is in the o■ state (hereinafter referred to as the "L" state), the NchFET (
51 is off. Next, the clock signal φ is “L”
When the Nc hFET (4J) is turned off and the inverted signal 7 of the clock signal φ becomes "H",
hFET (51) is turned on. Therefore, the contents of the first register circuit (31) are changed to the second register circuit (
Enter 32).

Thereafter, as the clock signal changes, the contents of the register circuit enter the register circuit on the right side.

However, in such a circuit, two types of clock signals, the clock signal φ and its inverted signal φ, are required in the shift register as described above.

[Summary of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to unify the clock input signal and thereby improve the circuit configuration. An object of the present invention is to provide a complementary semiconductor integrated circuit that is simplified and has an improved degree of integration.

In order to achieve such objects, the present invention utilizes NchFET
and PchFETs are alternately connected between register circuits as transmission gates.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a circuit diagram showing an embodiment of a complementary semiconductor integrated circuit according to the present invention, and shows an example in which the present invention is applied to a shift register circuit.

In FIG. 3, the same symbols as in FIGS. 1 and 2 indicate corresponding parts, (10) is NchFHT, (L
IJ is PchFET1Q21 is Nch FET,
These are alternately connected as transmission gates between register circuits (31) to (3n). And, these register circuits (31) to (3n) are NchFff
TQOJ, PcbFET(lυ, NchFET(
The gates of the pass control transistors are connected to the clock input terminals (71, (81, (
9) . . . , the odd-numbered pass control transistors are NchFETs, and the even-number pass control transistors are P ch F J ('I1.).

Next, the operation of the embodiment shown in FIG. 3 will be explained.

First, when the clock signal φ applied to the clock input terminals (71, (91) becomes "H" state, the NchFET (1
01 and Nch FET (121) are turned on.Then, the input signal from the data input terminal (1) is input to the first register circuit (31).At this time, the input signal from the clock input terminal (8) is input to the first register circuit (31). Since the applied clock signal φ is in the 'H' state, the PchFET (IIJ) is off, so the register contents of the first register circuit (31) are not propagated to the next register circuit (32).

Next, when the clock signal φ applied to the clock input terminal (8) becomes "L" state, the PchFET (14) shifts to the on state. And this PchFET (lυ
When turned on, the contents of the first register circuit (31) are propagated to the second register circuit (32).

At this time, since the clock signal φ applied to the clock input terminals (7) and (91) is in the L'' state, the NchFE
Since TQl (12) is off, the contents of the second register circuit (32) are not propagated to the next register circuit, and the contents of the first register circuit (31) are not propagated to the next register circuit.
No input signal enters from the data input terminal fil.

In this way, in the circuit of the embodiment shown in FIG. 3, the shift register can be operated by a single clock signal.

FIG. 4 is a circuit diagram showing another embodiment of the present invention, showing an example of a shift register circuit in which the storage circuit element in FIG. 3 is an inverter circuit.

In FIG. 4, parts that are the same as those in FIG. 3 are given the same reference numerals and explanations will be omitted. Q31, (+41 is complementary type M
The inverter circuit (131, (141) is connected in series by NchIi'ET (to), PchFET (Iυ) and NchFET (121).

Next, the operation of the embodiment shown in FIG. 4 will be explained.

First, the NCllFET (10) is turned on when the clock signal φ applied to its clock input terminal (7) is in the "H" state, and the input signal from the data input terminal fl) enters the inverter circuit α~. Next, this input signal is Nc
When the clock signal φ, which is held by the gate capacitance between hFETα0) and the inverter circuit (131) and is applied to the clock input terminal (8), is in the “L” state, PchFP3
Taυ is turned on, and the above data input signal is input to the inverter circuit (1 (a)).

Therefore, like the circuit shown in FIG. 3, the circuit of the embodiment shown in FIG. 4 is a shift register circuit that can be operated by a single clock signal. In the embodiment shown in FIG. 4, the memory circuit element is a complementary MO8.
It is an inverter circuit made up of circuits, and information is dynamically stored using the input capacitance of the inverter circuit.

In addition, P as in the embodiment shown in FIGS. 3 and 4 above
Simplification of the clock input signal by using a chFET and an NchFET in combination can also be used in a D-type flip-flop circuit. And in this case, PchFET
By using the NchFET and NchFET, the inverter between the two clock signal input transistors in the D-type flip-flop circuit can be omitted, and the degree of integration can be improved.

[Effects of the Invention] As explained above, according to the present invention, a C-MOS shift register circuit uses a PchFET and an NchFET as individual transmission gates, which is different from the conventional two.
Since the shift register circuit, which required various clock signals, is configured to operate with a single clock signal, the circuit configuration power is simplified, and the degree of integration is also improved accordingly.
The practical effects are extremely large. This method is extremely effective in that it eliminates the need for adjustment between clocks because a single clock signal is used.

As described above, according to the present invention, the conventional C-MOS of this type
It is unique as a complementary semiconductor integrated circuit, which has a greater effect than a shift register circuit and can unify the clock input signal.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing an example of a conventional C-MOS shift register, FIG. 3 is a circuit diagram showing an embodiment of a complementary semiconductor integrated circuit according to the present invention, and FIG. 4 is a circuit diagram showing an example of a complementary semiconductor integrated circuit according to the present invention. FIG. 7 is a circuit diagram showing another embodiment. (1)... life data input terminal, (2) fist... data output terminal, (31) to (3n)... register circuit (
memory circuit elements), (71 to (9)...clock input terminals, (101, (12)...NchFET (first
conductivity type MOS transistor), (IIJ --@@Pc
hFET (m 2 a% type MOS transistor), 0
3L (14)... In-tweeter circuit. Agent Masuo Oiwa, Commissioner of the Japan Patent Office 1. Indication of the case Japanese Patent Application No. 114601/1982 2, Title of the invention Complementary semiconductor integrated circuit 3, Person making the amendment Relationship to the case Patent applicant representative Hitoshi Katayama Department 4, agent Ill Claim of patent in the specification Scope column (1) Amend the claims in the specification as shown in the attached sheet. (21 Ibid., page 2, line 5, 1 structure)” followed by “(Hereinafter, C
(abbreviated as MO8)" is added. (3) “Circuit” on page 8, line 9 of the same book is “transistor”
and correct it. Attachment [(1) A logic circuit comprising a data input terminal to which a data input signal is applied, a data output signal from which a data output signal is obtained, and a clock input terminal to which a clock signal is applied, comprising complementary MOS transistors. at least two memory circuit elements consisting of at least two memory circuit elements, the memory circuit elements being coupled in series via a pass control type transistor, the gate of the pass control type transistor being connected to the clock input terminal, and Odd-numbered pass control transistors are composed of first conductivity type MOS transistors, and even-numbered pass control transistors are composed of second conductivity type MO8I.
- A complementary semiconductor integrated circuit characterized by being composed of transistors. (21) The storage circuit element is constituted by an inverter circuit formed of complementary MO8 transistors, and information storage is dynamically performed by the input capacitance of the inverter circuit. Complementary semiconductor integrated circuit as described in . ” or more - 808 -

Claims (2)

[Claims] (1) A logic circuit comprising a data input terminal to which a data input signal can be applied, a data output terminal to which a data output signal can be obtained, and a clock input terminal to which a clock signal can be applied, and comprising at least a complementary MOS transistor. It has two or more memory circuit elements, the memory circuit elements are coupled in series through pass control transistors, and the pass ff! The gate of the IIIm transistor is connected to the clock input terminal, and the j and tth pass control type transistors are covered by the 14th electric type MO8 transistor, and the even numbered pass control type transistors are connected to the second pass control type transistor.
A complementary semiconductor integrated circuit characterized in that it is composed of conductive MO8 transistors. (2) The storage circuit element is composed of an inverter circuit formed of complementary m and MO8 circuits, and the storage of information is dynamically performed depending on the input capacity of the inverter circuit. 11 Complementary semiconductor integrated circuit according to item 1 of value range.