JPS614979A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by providing each flip-flop circuit with a diagnosing circuit composed of two kinds of transmission gates, and cascading a diagnosing circuit and an information holding circuit between flip-flop circuits, and thus constituting a shift register. CONSTITUTION:Each flip-flop circuit of an information processing circuit is provided with a diagnosing circuit consisting of a latch circuit composed of a P- channel type transmission gate MOSFETQ23 which receives a diagnostic clock signal -phiS, N-channel type transmission gate MOSFETQ22, inverter circuit IV25, and feedback inverter circuit IV24. Then, respective flip-flop circuits are cascaded across a diagnostic circuit to constituted the shift register. Thus, elements signals are reduced in number to simplify the circuit constitution.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a semiconductor integrated circuit composed of MOSFETs (insulated gate field effect transistors), and is used for digital information processing such as gate arrays, etc. The present invention relates to a technique effective for use in a CMO8 (complementary MO3) integrated circuit device that constitutes a circuit.

[Background technology]

A digital information processing circuit performs a sequence operation for complex information processing by combining a gate circuit that takes information logic and a flip-flop circuit that holds its output signal in accordance with a predetermined clock signal. As shown in Figure 1, as a method for performing functional tests (operation diagnosis) on digital information processing circuits, each flip-flop circuit is provided with a diagnostic circuit as surrounded by a dotted line, and a plurality of flip-flop circuits are Configure a shift register between
It has been considered to examine the logical operation results in the gate circuits by serially taking out the information held in each flip-flop circuit.

However, when such diagnostic lfT functions are added,
As shown in the figure, there is a drawback that the number of elements becomes enormous. Also, to configure the shift register,
The above diagnostic circuit includes two-phase clock signals φsa and φS.
(For a technique that enables diagnosis of the gate circuit of a flip-flop circuit, see, for example, Japanese Patent Application No. 72884/1984).

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a flip-flop circuit having a diagnostic function with a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, for each flip-flop circuit included in the digital information processing circuit, a transmission gate MO3F of the first conductivity type controlled by a predetermined timing signal is connected to the input terminal of the information holding circuit in this flip-flop circuit.
ET, and a second conductivity type transmission gate MO3FET that receives the timing signal at the output terminal of the information retention circuit and transmits the signal at the output terminal of the information retention circuit to the latch circuit.
A shift register is constructed by providing a diagnostic circuit consisting of a plurality of flip-flop circuits, and arranging the diagnostic circuit and an information holding circuit in the flip-flop circuit in series between a plurality of flip-flop circuits. The figure shows a circuit diagram of an embodiment of a flip-flop circuit with a diagnostic function according to the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using known CMOS integrated circuit manufacturing techniques.

In the figure, one flip-flop circuit and its diagnostic circuit in the information processing circuit are shown as a representative. The flip-flop circuit of this embodiment includes a CMOS inverter circuit IV21 and an inverter circuit IV21 for (+i% return).
An information holding section is formed by a latch circuit in which input terminals and output terminals of 22 are cross-connected to each other.

An inverted output signal Q is sent from the output terminal of an inverter circuit IV21 in this latch circuit, and a non-inverted output signal Q is formed by an inverter circuit IV23 that receives this inverted signal Q.

The input circuit section in the flip-flop circuit is not particularly limited, but in order to simplify the circuit, a P-channel type input circuit section is provided between the data input signal and the input terminal of the latch circuit (information holding section). Transmission gate MO5FE
TQ20, clock signal GK and reset signal R are received, and the above transmission gate MO3FET is
a NAND gate circuit G that controls Q20;
It is composed of an N-channel MO3FETQ21 provided between the input terminal of the latch circuit and the ground potential point of the circuit, and an inverter circuit lV2O that receives the reset signal R and controls the MO5FETQ21. Such a Nant gate circuit G and inverter circuit lV2O are
It may also be used for other flip-flop circuits.

That is, the output signal of the Nant gate circuit G and the output signal of the inverter circuit rV20 may be commonly supplied to the gates of the corresponding MOSFETs of the input circuits in other flip-flop circuits.

In order to serially read out the information stored in the flip-flop circuit, a diagnostic circuit such as the circuit shown in the dotted line in the figure is provided. That is, a P-channel type transmission gate MOSFET Q23 receiving a diagnostic clock signal φS is provided between the input terminal Ds and the input terminal of the latch circuit constituting the information holding section of the flip-flop circuit. Further, another latch circuit is provided, which includes an inverter circuit IV25 similar to the information holding section constituting the flip-flop circuit and an inverter circuit IV24 for feedback, and this latch circuit and the output terminal (inverted output signal An N-channel type transmission gate MO'5FETQ22 receiving the clock signal φS is provided between the MO'5FETQ22 and Q).

A diagnostic circuit similar to that described above is also provided for each flip-flop circuit comprising an information holding section and an input circuit similar to that described above. The flip-flop circuits are connected in cascade via these diagnostic circuits. That is, for example, the input terminal Ds of the illustrated diagnostic circuit is connected to an external terminal of the semiconductor integrated circuit device, and the output terminal QS is connected to the input terminal Ds of the diagnostic circuit in the next-stage flip-flop circuit. . Thereafter, a plurality of flip-flop circuits are arranged in series in the same manner, and the output terminal Qs of the diagnostic circuit in the final stage flip-flop circuit is connected to an external terminal of the semiconductor integrated circuit device. This constitutes a shift register, and the information stored in each flip-flop circuit is serially sent out from the external terminal.

FIG. 3 shows a timing diagram for explaining an example of the operation of the above embodiment circuit.

In the figure, the timing diagram on the left side of the dotted line shows an example of the operation of a normal flip-flop circuit. That is, in normal operation mode, the diagnostic clock signal φ
With S set to high level, P in the diagnostic circuit
The channel type transmission gate MO3FETQ23 is in an off state, and the N channel type transmission gate MO3FETQ22 is in an on state.

On the other hand, when the flip-flop circuit is not in the reset state, the reset signal R is at a high level (logic "1"), so the Nant gate circuit G is kept open, and the clock signal CK is sent to the P channel. It is transmitted to the type transmission gate MO3FETQ20. Furthermore, due to the high level of the reset signal R, the inverter circuit lV2O
The output signal of becomes low level, and the reset MOS
FETQ21 is turned off.

Therefore, if the data input terminal is set to high level before the first clock signal CK arrives, the clock signal passed through the Nant gate circuit G becomes low level due to the high level of the clock signal GK, and the P-channel type Since the transmission gate MO8FETQ23 is turned off, the high level of the data signal is taken into the information holding section.

As a result, the non-inverted output signal Q changes to high level and the inverted output signal Q changes to low level.

Next, when the reset signal R is set to a low level, the AND gate circuit G is closed and its output is set to a high level regardless of the clock signal GK, so that the P-channel type transmission gate MO3FET Q20 is turned off. .

Furthermore, the low level of the reset signal R causes the output signal of the inverter circuit 1V2O to go high, so the MO3FETQ21 turns on and supplies a low level to the input terminal of the information holding section. As a result, the non-inverted output signal Q is reset to low level and the inverted output signal Q is reset to high level.

When the reset signal R returns to high level, data input signals are taken in according to the clock signal CK. For example, if the data input signal 1 remains at a high level, the first clock signal CK after the reset signal 100 is set to a high level causes the non-inverted output signal Q to go high and the inverted output signal Q to a low level. be done.

In addition, the N-channel type transmission gate MO3 for the above diagnosis
Since the FET Q22 is turned on, the output signal Qs of the latch circuit of the diagnostic circuit changes in accordance with the change in the inverted output signal Q. However, since the P-channel transmission gate MOSFET (corresponding to Q23) that constitutes the input section of the diagnostic circuit connected to the next stage is in the off state, A shift operation of stored information is never performed.

Next, in the function test (during operation diagnosis), the clock signal C
K is fixed at a low level and the information processing sequence is stopped. In this way, the output signal of the Nant gate circuit G becomes high level, so that the P-channel type transmission gate MO3FETQ20 is turned off.

When the diagnostic shift clock signal φS is at a high level, the memory information in the flip-flop circuit is
? (In the figure, the same low level as the inverted signal) has already been taken into the latch circuit, and the output signal Qs has become high level. Next, when the clock signal φS is set to low level, the P-channel type transmission gate 1-M0 SF, ETQ
23 is in an on state, so if the information held in the previous stage flip-flop circuit is at a low level, this low level is taken into the information holding section of the flip-flop circuit. This low level is sent from the output terminal Qs to the next stage when the clock signal φS changes to high level. By repeating similar operations, the information stored in each flip-flop circuit is serially transferred and sent out from the external terminal.

Note that the above shift operation destroys the stored information and moves to L7, so if the information processing sequence is to continue, the stored information taken out from the external terminal is transferred to the diagnostic input terminal Ds in the first-stage flip-flop circuit.
The original stored information can be recovered by supplying the expected value to the terminal Ds or serially supplying the expected value from this terminal Ds. Thereby, the operation can be continued from the stopped information processing step.

〔effect〕

(1) By using a transmission gate MO8FET composed of a P-channel MO3FET and an N-channel inter-O8FET as a diagnostic circuit for connecting flip-flop circuits included in an information processing circuit in a cascade configuration,
A shift operation can be performed using one shift clock. This provides the effect of reducing the number of elements and the number of signals.

(2) By using one transmission gate MO3FET and an AND circuit that receives a clock signal and a reset signal to control the transmission gate MOSFET as an input circuit constituting the flip-flop circuit, the flip-flop circuit itself can be simplified. This has the effect of making it possible to improve the

(3) The effects of ill and (2) above can be combined to achieve the effect that a significant reduction in the number of elements can be achieved.

(4) Along with the reduction in the number of elements according to (11 to 3) above, the effect that the wiring thereof can also be reduced can be obtained.

(5) With the above (11 to (4)), it is possible to achieve the effect that a high degree of integration can be achieved in a digital semiconductor integrated circuit device including a large number of flip-flop circuits.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the flip-flop circuit can take various embodiments depending on its usage, such as one having both set/reset functions as shown in FIG. Furthermore, the P-channel MO8FET and the N-channel/L/MO3FET may be configured in reverse. In this case, if the level of the clock signal is reversed, the same operation will be performed. Further, the latch circuit in the diagnostic circuit may be a simple inverter circuit. Since the diagnostic circuit performs a shift operation according to the shift clock signal φS, the necessary information retention operation can be achieved even by utilizing the operation of accumulating charges in the input capacitor in the inverter circuit.

[Application field]

The present invention can be widely used in digital semiconductor integrated circuit devices that are configured with, for example, gate arrays and perform various information processing operations such as small and medium-sized computers.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a flip-flop circuit with a diagnostic function that was considered prior to the present invention; FIG. 2 is a circuit diagram showing an example of a flip-flop circuit with a diagnostic function according to the present invention; FIG. 3 is a timing diagram showing an example of the operation. IVI~IV25...CMOS inverter circuit, G...
nant gate circuit

Claims (1)

[Claims] 1. For a flip-flop circuit included in a digital information processing circuit, a first conductivity type that is provided at an input terminal of an information holding circuit in this flip-flop circuit and controlled by a predetermined timing signal. Transmission gate MOSF
ET, a second conductivity type transmission gate MOSFET provided at the output terminal of the information holding circuit and transmitting the signal of the output terminal of the information holding circuit in response to the timing signal, and a signal passing through the transmission gate MOSFET. A semiconductor integrated circuit characterized in that a diagnostic circuit including a holding latch circuit is provided, and a shift register is configured between a plurality of flip-flop circuits by the diagnostic circuit and an information holding circuit in the flip-flop circuit. Device. 2. The semiconductor integrated circuit device according to claim 1, wherein the digital information processing circuit is constituted by a CMOS circuit. 3. The input section of the flip-flop circuit is a first conductivity type transmission gate MOSFE that transmits the input signal to the information holding section.
T, a logic gate circuit that receives a clock signal and a reset signal and transmits the output signal to the gate of the transmission gate MOSFET, and is provided between the input terminal of the information holding circuit and the power supply voltage or the ground potential point of the circuit. and a MOSFET that operates in response to an inverted signal of the reset signal, and the information holding section is comprised of a latch circuit consisting of an output CMOS inverter and a feedback CMOS inverter. A semiconductor integrated circuit device according to claim 1 or 2.