JPS6077434A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6077434A
JPS6077434A JP58188092A JP18809283A JPS6077434A JP S6077434 A JPS6077434 A JP S6077434A JP 58188092 A JP58188092 A JP 58188092A JP 18809283 A JP18809283 A JP 18809283A JP S6077434 A JPS6077434 A JP S6077434A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
insulating substrate
semiconductor
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58188092A
Other languages
Japanese (ja)
Inventor
Takayoshi Kawakami
川上　隆由
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58188092A priority Critical patent/JPS6077434A/en
Publication of JPS6077434A publication Critical patent/JPS6077434A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To readily isolate an improper semiconductor chip by providing a projection on an insulating substrate as a mounting pad. CONSTITUTION:A projection 22a is formed directly under a semiconductor chip 3 on an insulating substrate 11, an area of a mounting pad A is smaller than that of the chip 3, and the peripheral edges of the four sides of the chip 3 are projected from the pad A. When the substrate 11 is heated and the outer peripheral edges of the chip 3 are lifted from below by a jig, it can be readily removed without crack of the chip. According to this construction, the cost of the product can be reduced in a hybrid IC of high density multichip type.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、最近の半導体装置の高密度実装化傾向に適
合するように、回路構成後洗発見さねた不良半導体チッ
プの交換が容易になるよう医、半導体チップとその取付
はパット部との構成時における相互の寸法関係にあらか
じめ引剥しのための〔従来技術〕 第１図は従来の半導体装置を示すものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention facilitates the replacement of defective semiconductor chips that are not found after circuit configuration, in order to comply with the recent trend toward high-density packaging of semiconductor devices. 2. Prior Art FIG. 1 shows a conventional semiconductor device.

この図において、１はセラミック等からなる絶縁基板、
２は導電パターンを形成する電極、３は半導体チップ、
４はこの半導体チップ３ケ絶縁基板１上のその取付はバ
ット部Ａ上に機械的、電気的に接続するための接着剤、
５は前記半導体チップ３と電極２とを接続する金線であ
る。In this figure, 1 is an insulating substrate made of ceramic or the like;
2 is an electrode forming a conductive pattern; 3 is a semiconductor chip;
4 is an adhesive for mechanically and electrically connecting the three semiconductor chips to the butt part A for mounting them on the insulating substrate 1;
Reference numeral 5 denotes a gold wire connecting the semiconductor chip 3 and the electrode 2.

一般に、混成集積回路装置とかマルチチップＩＣ等の半
導体装置の製造工程においては、目視検査または中間電
気試験により半導体チップ３の傷、電気的接続不良ある
いに接着不良が発見された場合は、こｈ４．不良品とし
て廃却するか、または当該半導体チップ３’／交換する
方法があるが、集積回路装置の種類の規模が拡太さねた
高密度実装の現状では、コストとの兼ね合いから後者の
半導体チップ交換作業が必要となってきている。Generally, in the manufacturing process of semiconductor devices such as hybrid integrated circuit devices and multichip ICs, if scratches, electrical connections, or adhesion defects on the semiconductor chip 3 are found through visual inspection or intermediate electrical tests, this will occur. h4. There are two methods: to discard the semiconductor chip as a defective product or to replace the semiconductor chip, but in the current situation of high-density packaging where the types of integrated circuit devices have not expanded in scale, the latter method is recommended due to cost considerations. Chip replacement work is becoming necessary.

ところで、このような半導体装ｆｉにおいて、不良半導
体チップ乞交換するには、絶縁基板１ケ全接着剤４の接
着強度ン低下させ、半導体装ツブ３と接着剤４との接着
部をその側方より機械的に押すことにエリ、不良半導体
チップを取り除いていた。By the way, in order to replace a defective semiconductor chip in such a semiconductor device fi, the adhesive strength of the entire adhesive 4 on one insulating substrate is reduced, and the bonded portion between the semiconductor chip 3 and the adhesive 4 is removed from its side. By using a more mechanical press, the defective semiconductor chips were removed.

このように取り除き作業は、半導体チップ３の接着部を
側方より押すことになるために、具体的にはＬＳＩチッ
プのようなものを取り除こうとすると、１０ｋ１７以上
の力を要し、こねかため専用治具な用いてもその取り除
き作業が非常に困難であった。In this way, the removal work involves pushing the adhesive part of the semiconductor chip 3 from the side, so if you try to remove something like an LSI chip, it will require a force of 10k17 or more, and it will be hard to knead. Even if a special jig was used, it was extremely difficult to remove it.

これは半導体チップ３の厚みが２５０ミクロン〜５００
ミクロンと薄いこと、半導体チップ側面（切断面）がそ
れ自体の結晶面により斜めになっていたりして、加えら
第１た力により斜めに割れてしまうということからであ
る。This means that the thickness of the semiconductor chip 3 is between 250 microns and 500 microns.
This is because the semiconductor chip is as thin as a micrometer and the side surface (cut surface) of the semiconductor chip is oblique due to its own crystal plane, so that the applied force will cause it to break diagonally.

なお、現在では、接着強度がより強いものが採用され、
例えば３５０℃で３０分間加熱した場合においても接着
強度の劣化が少ない接着剤を用いる傾向から、取り除き
作業をより困難にしているという欠点があった。Currently, products with stronger adhesive strength are used,
For example, there is a tendency to use adhesives that exhibit less deterioration in adhesive strength even when heated at 350° C. for 30 minutes, making removal work more difficult.

〔発明の概要〕 この発明は、上記のような従来のものの欠点ｌ除去する
ためＫなさねたもので、取＋ｊ１ナパット部として絶縁
基板に突出部を形成し半導体チップと取付はバット部と
の相互の寸法関係？生成不良半導体チップが容易に交換
できるようにしたものである。[Summary of the Invention] The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional product, and the semiconductor chip is attached to the butt part by forming a protruding part on the insulating substrate as a mounting part. Mutual dimensional relationship? This allows defective semiconductor chips to be easily replaced.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について説明する。 An embodiment of the present invention will be described below.

第２図はこの発明の一実施例を示す側断面図で、第１図
と同一個所は同一符号で示している。絶縁基板１１の中
央には、半導体チップ３の直下に位置するように突出部
１１ｍを形成させ、かつ、この突出ｍ１ｌａを含めた半
導体装ツブ３の取付け／くント部への縦横寸法は、その
上に接着剤４で固着した半導体チップ３０ａｍ寸法より
小さくシ。FIG. 2 is a side sectional view showing an embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same symbols. A protrusion 11m is formed in the center of the insulating substrate 11 so as to be located directly below the semiconductor chip 3, and the vertical and horizontal dimensions of the mounting/mounting part of the semiconductor chip 3 including the protrusion m1la are as follows. The size of the semiconductor chip 30am is smaller than the size of the semiconductor chip fixed with adhesive 4 on top.

当該半導体チップ３の四辺の外周縁部を取付はバット部
Ａ外に突出させている点に特徴ケ有するものである。The semiconductor chip 3 is characterized in that the outer periphery of the four sides of the semiconductor chip 3 protrudes outside the butt part A.

このようにして、回路構成後に不具合が発見された、い
わゆる不良半導体チップを交換する場合には、従来の方
法と同様に絶縁基板を全体的若しくは局部的に加熱し、
半導体チップ３の突出外周縁部を引剥し治具の当て代と
して核部を下面から押し上げることが可能になるように
し、半導体チップ３の割ねを生することな（容易に取り
除くことができるようにしたものである。In this way, when replacing a so-called defective semiconductor chip in which a defect was discovered after the circuit was configured, the insulating substrate is heated entirely or locally as in the conventional method.
The protruding outer peripheral edge of the semiconductor chip 3 is used as an allowance for the peeling jig so that the core can be pushed up from the bottom surface without causing any cracking of the semiconductor chip 3 (so that it can be easily removed). This is what I did.

なお、取付はバット部Ａ外に突出させる半導体チップ３
の外周縁部は必すしも四辺でなくとも前後あるいは左右
の二辺であつあもｊ、（・。Note that the semiconductor chip 3 is mounted to protrude outside the butt part A.
The outer periphery of is not necessarily on all four sides, but may be on the front and back or on the left and right sides.

〔発明の効果〕〔Effect of the invention〕

以上説明したよ５ＶＣ１この発明は、半導体チップより
その取利ロパット部を突出部とし、そσ〕面積を半導体
チップより小さくして、半導体クーツブの外周縁部を取
付はノくント部外に突出させて（・るりで、不良半導体
チップが発見された場合その引剥しが容易にでき、その
部分の交換グ）みですむので、特に作業ミスの多（なる
高密度のマルチチップ型理＃：集積回路装置にこの発明
を採用すること利点がある。As explained above, 5VC1 In this invention, the mounting area of the semiconductor chip is made to be a protruding part, the area is smaller than that of the semiconductor chip, and the outer peripheral edge of the semiconductor chip is protruded outside the mounting part. If a defective semiconductor chip is found, it can be easily removed and the part replaced. There are advantages to employing the invention in integrated circuit devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置における半導体チップの取付
はバット部を示１−側断面図、第２図し工この発明の一
実施例を示す側断面−である。 図中、１は絶縁基板、３は半導体チップ、４番１接着剤
、１１＆は突出部、Ａは取付はパント部である。 なお、図中の同一符号はβ１−または相当部分ケ示す。 代理人　大岩増雄　Ｃ外２名） 手続補正書（自発） 昭和オ？年タ月／７日 特許庁長官殿　間色 １、事件の表示　特願昭５８−１８８０９２号２、発明
の名称　半導体装置 ３、補正をする者 ５、補正の対象 明細書の発明の詳細な説明の欄 ６、補正の内容 明細書第２頁１５行の１種類」を、「回路」と補正する
。 以上FIG. 1 is a side sectional view showing a butt portion for mounting a semiconductor chip in a conventional semiconductor device, and FIG. 2 is a side sectional view showing an embodiment of the present invention. In the figure, 1 is an insulating substrate, 3 is a semiconductor chip, 4 is an adhesive, 11 & is a protruding portion, and A is a punt portion for mounting. Note that the same reference numerals in the figures indicate β1- or corresponding parts. Agent: Masuo Oiwa, 2 persons other than C) Procedural amendment (voluntary) Showa O? To the Commissioner of the Japan Patent Office, January 7th, 2016, Maishiro 1, Indication of the case: Japanese Patent Application No. 188092/1988 2, Title of the invention: Semiconductor device 3, Person making the amendment 5, Detailed explanation of the invention in the specification to be amended Column 6, "One type" on page 2, line 15 of the detailed description of the amendment, is corrected to "circuit."that's all

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ！固着する取付はパット部として絶縁基板
に突出部ケ形成し、この突出部の前記半導体チップを固
着する部分の面′ｆＲを前記半導体チップの面積より小
さく形成して、この半導体チップの外周縁部を前記取付
はパット部外に突出させ、この突出させた部分で不良半
導体チップヶ引剥し治具の当て代を形成させたことを％
徴とする半導体装置。Semiconductor chip! For fixing, a protruding part is formed on the insulating substrate as a pad part, and the surface 'fR of the part of the protruding part to which the semiconductor chip is fixed is formed to be smaller than the area of the semiconductor chip, and the outer peripheral edge of the semiconductor chip is The above-mentioned attachment was made to protrude outside of the pad part, and this protruding part formed the allowance for the defective semiconductor chip peeling jig.
Semiconductor device with special characteristics.
JP58188092A 1983-10-04 1983-10-04 Semiconductor device Pending JPS6077434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58188092A JPS6077434A (en) 1983-10-04 1983-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58188092A JPS6077434A (en) 1983-10-04 1983-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6077434A true JPS6077434A (en) 1985-05-02

Family

ID=16217558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58188092A Pending JPS6077434A (en) 1983-10-04 1983-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6077434A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137170A (en) * 1996-08-20 2000-10-24 Nec Corporation Mount for semiconductor device
WO2004074168A3 (en) * 2003-02-20 2005-04-14 Analog Devices Inc Packaged microchip with thermal stress relief
US6946742B2 (en) 2002-12-19 2005-09-20 Analog Devices, Inc. Packaged microchip with isolator having selected modulus of elasticity
US7166911B2 (en) 2002-09-04 2007-01-23 Analog Devices, Inc. Packaged microchip with premolded-type package
US8344487B2 (en) 2006-06-29 2013-01-01 Analog Devices, Inc. Stress mitigation in packaged microchips
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
US10131538B2 (en) 2015-09-14 2018-11-20 Analog Devices, Inc. Mechanically isolated MEMS device
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US11417611B2 (en) 2020-02-25 2022-08-16 Analog Devices International Unlimited Company Devices and methods for reducing stress on circuit components
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture
US12612303B2 (en) 2022-01-25 2026-04-28 Analog Devices, Inc. Stress isolation for integrated circuit package integration

Cited By (14)

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