JPS607752A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS607752A JPS607752A JP58115566A JP11556683A JPS607752A JP S607752 A JPS607752 A JP S607752A JP 58115566 A JP58115566 A JP 58115566A JP 11556683 A JP11556683 A JP 11556683A JP S607752 A JPS607752 A JP S607752A
- Authority
- JP
- Japan
- Prior art keywords
- lead wire
- semiconductor element
- semiconductor device
- wire terminals
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
Cal 発明の技術分野
本発明は、半導体装置に係り、特に、リード線端子導出
部の構成およびその製造方法に関す。DETAILED DESCRIPTION OF THE INVENTION Cal Technical Field of the Invention The present invention relates to a semiconductor device, and in particular to a structure of a lead wire terminal lead-out portion and a method of manufacturing the same.
(b) 技術の背景
半導体装置の高性能化が進むに従い、半導体素子内の回
路集積度が上がり、発熱量が増加している。これに対処
するため、効果的な放熱が可能である構成がめられてい
る。(b) Background of the Technology As the performance of semiconductor devices progresses, the degree of circuit integration within semiconductor elements increases and the amount of heat generated increases. In order to deal with this, configurations that can effectively dissipate heat are being developed.
キャビティダウン(Cavity Dos*n )方式
は、この−環として出現して来たもので、その優れた放
熱効果は、優れた半導体装置の実用化に寄与している。The cavity down (Cavity Dos*n) method has emerged as a solution to this problem, and its excellent heat dissipation effect has contributed to the practical application of excellent semiconductor devices.
fc) 従来技術と問題点
第1図(alは従来のキャビティダウン方式による半導
体装置の一例の構成図、第1図(b)はそのパッケージ
本体の構成図で、1はパッケージ本体、2は基板、2a
はキャビティ、3a・3bはリード線端子、4a・4b
は導体パターン、5は半導体素子、6はワイヤ、7はカ
バー、8はヒートシンクをそれぞれ示す。fc) Prior art and problems Figure 1 (Al is a block diagram of an example of a semiconductor device using the conventional cavity down method, Figure 1 (b) is a block diagram of the package body, 1 is the package body, 2 is the substrate , 2a
is the cavity, 3a and 3b are lead wire terminals, 4a and 4b
5 represents a conductor pattern, 5 represents a semiconductor element, 6 represents a wire, 7 represents a cover, and 8 represents a heat sink.
多層セラミックでなり、複数のリード線端子3a・3b
等を基板2の面に対して略垂直に植設している基板2に
、半導体素子5を搭載するため設けられたキャビティ2
aは、リード線端子3a・3b等が突出している主面側
に開口し、キャビティ2aの底面にあって半導体素子5
が接合されるバッドは、リード線端子例えば3aに導体
パターン4aで接続されており、他のリード線端子例え
ば3b等は、半導体素子5にワイヤ6で接続される回路
導出バンドに導体パターン4bで接続されていて、第1
図(b)に示すパンケージ本体1が、−個の完成部品と
なっている。Made of multilayer ceramic, multiple lead wire terminals 3a and 3b
A cavity 2 provided for mounting a semiconductor element 5 on the substrate 2 in which the semiconductor elements 5 and the like are implanted substantially perpendicularly to the surface of the substrate 2.
A is open on the main surface side from which the lead wire terminals 3a, 3b, etc. protrude, and is located on the bottom surface of the cavity 2a, and is open to the semiconductor element 5.
The pad to be bonded is connected to a lead wire terminal, e.g. 3a, with a conductor pattern 4a, and other lead wire terminals, e.g. 3b, etc. are connected to a circuit lead-out band connected to the semiconductor element 5 with a wire 6, with a conductor pattern 4b. connected and first
The pan cage main body 1 shown in Figure (b) has - pieces of completed parts.
これを、半導体装置に組上げるには、半導体素子5をキ
ャビティ2aの底面に載置接合した後、半導体素子の回
路導出パッドとパッケージ本体1の前記回路導出パッド
とをワイヤ6で接続して、半導体素子5の搭載を済ませ
、キャビティ2aを封止するためカバー7をキャビティ
2aの開口に被せ基板2と接合して、半導体装置本体を
完成させ、続いて、基板2の、キャビティ2aの背面部
分にヒートシンク8を取付けて、第1図(a)に示す半
導体装置を完成させる。To assemble this into a semiconductor device, after placing and bonding the semiconductor element 5 on the bottom surface of the cavity 2a, the circuit lead-out pad of the semiconductor element and the circuit lead-out pad of the package body 1 are connected with the wire 6. After mounting the semiconductor element 5, a cover 7 is placed over the opening of the cavity 2a to seal the cavity 2a, and the cover 7 is bonded to the substrate 2 to complete the semiconductor device body. A heat sink 8 is attached to the substrate to complete the semiconductor device shown in FIG. 1(a).
この、キャビティダウン方式になっている半導体装置は
、半導体素子5と基板2の薄く形成された部分の面、お
よび、基板2のその背面とヒートシンク8とが、全て面
で接合されているため、半導体素子50表面で発生した
熱は、効果的にヒートシンク8へ伝達されて優れた放熱
機能を持つが、前記半導体素子5をパッケージ本体1に
搭載する作業、特に、ワイヤ6で前記両バンドを接続す
る作業は、基板2に植設されているリード線端子3a・
3b等が邪魔になり、極めて困難である欠点がある。In this cavity-down type semiconductor device, the semiconductor element 5 and the thinly formed surface of the substrate 2, as well as the back surface of the substrate 2 and the heat sink 8, are all bonded to each other at their surfaces. The heat generated on the surface of the semiconductor element 50 is effectively transferred to the heat sink 8 and has an excellent heat dissipation function, but the work of mounting the semiconductor element 5 on the package body 1, especially connecting the two bands with the wire 6, is difficult. The work to be done is to connect the lead wire terminals 3a and 3a implanted on the board 2.
3b etc. are in the way and have the disadvantage of being extremely difficult.
(dl 発明の目的
本発明の目的は上記従来の欠点に鑑み、リー線端子に邪
魔されないで、半導体素子の搭載が可能である、キャビ
ティダウン方式半導体装置の構成およびその製造方法を
提供するにある。(dl) Purpose of the Invention In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a structure of a cavity-down type semiconductor device and a method for manufacturing the same, in which a semiconductor element can be mounted without being obstructed by a lead wire terminal. .
(Q) 発明の構成
上記目的は、半導体素子を搭載するパッケージ本体にお
いては、複数なるリード線端子を導出させる個々の導出
部にリード線端子挿入用貫通孔を形成し、該貫通孔を内
面には該パンケージ本体内の内部配線に接続された導体
膜が形成されていて、且つ、該パッケージ本体の主面お
よび裏面のどちらからでも該リード線端子が挿入可能で
あるものにしておき、該パッケージ本体に前記半導体素
子を搭載し、所要の封止等を行った後に、前記複数なる
リード線端子を咳M通孔に挿入固着させる、また、要す
れば、複数なる前記リード線端子を、予め、絶縁板で相
互に固着しておき、前記複数なるリード線端子を前記貫
通孔に一括挿入固着させる本発明の構成によって達成さ
れる。(Q) Structure of the Invention The above object is to form a through hole for inserting a lead wire terminal in each lead-out portion from which a plurality of lead wire terminals are led out in a package body in which a semiconductor element is mounted, and to insert the through hole into the inner surface. The package has a conductive film connected to the internal wiring in the package body, and the lead wire terminal can be inserted from either the main surface or the back surface of the package body. After mounting the semiconductor element on the main body and performing necessary sealing, etc., the plurality of lead wire terminals are inserted and fixed into the cough M through holes, and if necessary, the plurality of lead wire terminals are This is achieved by the structure of the present invention, in which the plurality of lead wire terminals are fixed to each other with an insulating plate, and the plurality of lead wire terminals are inserted and fixed into the through hole at once.
この構成によれば、半導体素子の搭載時にはリード線端
子が存在しないので、その作業は容易であり、前記リー
ド線端子の突出する部分を、前記パッケージ本体の主面
側である半導体素子搭載面側に位置させて挿入固着すれ
ば、所望のキャビティダウン方式となる。According to this configuration, since there are no lead wire terminals when mounting a semiconductor element, the work is easy, and the protruding portion of the lead wire terminal is placed on the semiconductor element mounting surface side which is the main surface side of the package body. If it is inserted and fixed at the position, the desired cavity down method will be achieved.
更に、前記リード線端子の突出する部分を、裏面側に位
置させて挿入固着すれば、キャビティアップ(Cavi
ty Up )方式となり、部品の共通化にも寄与でき
る。Furthermore, by positioning the protruding portion of the lead wire terminal on the back side and inserting and fixing it, it is possible to open the cavity.
ty Up) method, which can also contribute to the standardization of parts.
また、半導体素子の搭載・封止の工程は、パンケージ本
体にはリード線端子の如き異形をなす突起物がないので
、組立自動化もやり易くなる利点がある。Furthermore, since there are no abnormally shaped protrusions such as lead wire terminals on the pancage body, the process of mounting and sealing the semiconductor elements has the advantage of being easier to automate assembling.
(fl 発明の実施例
以下本発明の実施例を図により説明する。全図を通じ同
一符号は同一対象物を示す。(fl Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same reference numerals indicate the same objects throughout the drawings.
第2図は本発明の構成によるパフケージ本体の一例の構
成図、第3図は同じく半導体装置本体の構成図、第4図
は同じくリード線端子組立の構成図、第5図(a)・第
5図(b)は同じくキャビティダウン方式である半導体
装置完成の構成図、第6図(a)・第6図(blは同じ
くキャビティア・ノブ方式である半導体装置完成の構成
図で、9は絶縁板、11は、<ソケージ本体、12は基
板、12a、はキャビティ、13a13bは貫通孔、1
4a 44bは導体パターン、20は半導体装置本体、
21はリード線端子組立、23a・23bはリード線端
子、24a ・24bは挿着部、25a ・25bは突
出部をそれぞれ示す。FIG. 2 is a block diagram of an example of a puff cage main body according to the present invention, FIG. 3 is a block diagram of a semiconductor device main body, FIG. 4 is a block diagram of a lead wire terminal assembly, and FIGS. Figure 5 (b) is a block diagram of a completed semiconductor device that also uses the cavity down method, Figures 6 (a) and 6 (bl) are block diagrams of a completed semiconductor device that also uses the cavity-knob method, and 9 is a block diagram of a completed semiconductor device that also uses the cavity-down method. An insulating plate, 11 is a socket body, 12 is a substrate, 12a is a cavity, 13a and 13b are through holes, 1
4a and 44b are conductor patterns, 20 is a semiconductor device body,
21 is a lead wire terminal assembly, 23a and 23b are lead wire terminals, 24a and 24b are insertion portions, and 25a and 25b are protruding portions, respectively.
第2図に示すパッケージ本体11は、第1図山)に示す
パッケージ本体1におけるリード線端子3a・3b等を
除去し、代わりに、その導出部に、リード線端子がパッ
ケージ本体11の主面及び裏面のどちらからも略垂直に
挿入可能であって、内面に導体膜を有する複数の貫通孔
13a ・13b等を形成したものである。そして、第
1図(b)の場合と同様に、貫通孔例えば13aの導体
膜は導体パターン14aに、他の貫通孔13b等の導体
膜は導体パターン14bに接続されている。In the package body 11 shown in FIG. 2, the lead wire terminals 3a, 3b, etc. in the package body 1 shown in FIG. It can be inserted substantially vertically from either the top or the rear surface, and has a plurality of through holes 13a, 13b, etc., each having a conductive film on the inner surface. As in the case of FIG. 1(b), the conductor film in the through hole 13a, for example, is connected to the conductor pattern 14a, and the conductor films in other through holes 13b, etc. are connected to the conductor pattern 14b.
半導体装置を組上げる手順は次のようにする。The procedure for assembling the semiconductor device is as follows.
最初は、半導体素子5をキャビティ12aの底面に載置
接合し、ワイヤ6で接続する半導体素子5の搭載を済ま
せ、カバー7でキャビティ12aを封止して第3図に示
す半導体装置本体20を完成させる。この作業内容は、
第1図(alの場合と同様であるが、リード線端子の如
く作業の邪魔になるものが無く平板状であるため、作業
は容易であり、自動化もやり易い。First, the semiconductor element 5 is placed and bonded on the bottom surface of the cavity 12a, and the semiconductor element 5 connected with the wire 6 is mounted.The cavity 12a is sealed with the cover 7, and the semiconductor device main body 20 shown in FIG. 3 is completed. Finalize. This work includes:
Fig. 1 (Similar to the case of al), but since there is no obstacle such as a lead wire terminal that gets in the way of the work, and the work is flat, the work is easy and automation is easy.
続いて、第5図(a)のように、リード線端子23a・
23b等の、突出させる突出部25a ・25b等をキ
ャビティ12aの開口側に位置させて、挿着部24a・
24b等を、パッケージ本体11の貫通孔13a ・1
3b等に挿入固着させ、反対側にヒートシンク8を取付
けて、キャビティダウン方式の半導体装置を完成させる
。Next, as shown in FIG. 5(a), the lead wire terminals 23a and
The protruding parts 25a, 25b, etc., such as 23b, are positioned on the opening side of the cavity 12a, and the insertion parts 24a, 25b, etc. are positioned on the opening side of the cavity 12a.
24b, etc., into the through hole 13a/1 of the package body 11.
3b and the like, and a heat sink 8 is attached to the opposite side to complete a cavity down type semiconductor device.
複数なるリード線端子23a ・23b等の挿入固着を
一括して行いたい場合には、第4図に示すリード線端子
組立21を用意すれば良い。これは、リード線端子23
a ・23b等が、貫通孔13a ・13bの配列に合
致させた配置になって、その、挿着部24a・24b等
と、突出部25a ・25b等との開示、絶縁材でなる
絶縁板9で相互に固着されているもので、これを使用し
た場合の半導体装置完成は第5図(b)の如くなる。If it is desired to insert and fix a plurality of lead wire terminals 23a, 23b, etc. all at once, a lead wire terminal assembly 21 shown in FIG. 4 may be prepared. This is the lead wire terminal 23
a, 23b, etc. are arranged to match the arrangement of the through holes 13a, 13b, and the insertion portions 24a, 24b, etc., and the protruding portions 25a, 25b, etc. are disclosed, and the insulating plate 9 is made of an insulating material. When these are used, the completed semiconductor device is as shown in FIG. 5(b).
以上の構成において、リード線端子23a ・23b等
の突出部25a ・25b等をキャビティ12aの開口
側と反対に位置させて、挿入固着すれば、第6図(a)
・第6図(blのように、キャビティア・ノブ方式の半
導体装置にすることができる。従って、本発明の構成で
は、両方式で、部品の共通化を図ることも可能である。In the above configuration, if the protrusions 25a, 25b, etc. of the lead wire terminals 23a, 23b, etc. are positioned opposite to the opening side of the cavity 12a and inserted and fixed, as shown in FIG. 6(a).
- As shown in FIG. 6 (bl), it is possible to use a cavity-knob type semiconductor device. Therefore, with the configuration of the present invention, it is also possible to use common parts for both types.
(gl 発明の効果
以上に説明したように、本発明による構成によれば、リ
ード線端子に邪魔されないで半導体素子の搭載が可能で
ある、キャビティダウン方式半導体装置の構成およびそ
の製造方法が提供出来、更に、キャビティアップ方式と
の部品の共通化も可能になり、半導体装置の製造安定化
を可能にさせる効果がある。(gl Effects of the Invention As explained above, according to the structure of the present invention, it is possible to provide a structure of a cavity-down type semiconductor device and a manufacturing method thereof, in which a semiconductor element can be mounted without being obstructed by lead wire terminals. Furthermore, it becomes possible to share parts with the cavity-up method, which has the effect of making it possible to stabilize the production of semiconductor devices.
第1図(alは従来のキャビティダウン方式による半導
体装置の一例の構成図、第1図(6)はそのパッケージ
本体の構成図、第2図は本発明の構成によるパンケージ
本体の一例の構成図、第3図は同じ(半導体装置本体の
構成図、第4図は同じ(リード線端子組立の構成図、第
5図(a)・第5図(b)は同じくキャビティダウン方
式である半導体装置完成の構成図、第6図(a)・第6
図1b)は同じくキャビティアップ方式である半導体装
置完成の構成図である。
図面において、1はパンケージ本体、2は基板、2aは
キャビティ、3a・3bはリード線端子、4a・4bは
導体パターン、5は半導体素子、6はワイヤ、7はカバ
ー、8はヒートシンク、9は絶縁板、11はパッケージ
本体、12は基板、12aはキャビティ、13a・13
bは貫通孔、14a 44bは導体パターン、20は半
導体装置本体、21はリード線端子組立、23a−23
bはリード線端子、24a ・24bは挿着部、25a
・25bは突出部をそれぞれ示す。
第4−回FIG. 1 (Al is a configuration diagram of an example of a semiconductor device using the conventional cavity down method, FIG. 1 (6) is a configuration diagram of its package body, and FIG. 2 is a configuration diagram of an example of a pan cage body according to the configuration of the present invention. , Fig. 3 is the same (configuration diagram of the semiconductor device main body, Fig. 4 is the same (configuration diagram of lead wire terminal assembly, Fig. 5 (a) and Fig. 5 (b) is the same semiconductor device of the cavity down method. Completed configuration diagram, Figure 6 (a), Figure 6
FIG. 1b) is a diagram illustrating the completed structure of a semiconductor device also using the cavity-up method. In the drawings, 1 is a pan cage body, 2 is a substrate, 2a is a cavity, 3a and 3b are lead wire terminals, 4a and 4b are conductor patterns, 5 is a semiconductor element, 6 is a wire, 7 is a cover, 8 is a heat sink, and 9 is a Insulating plate, 11 is the package body, 12 is the substrate, 12a is the cavity, 13a.
b is a through hole, 14a 44b is a conductor pattern, 20 is a semiconductor device body, 21 is a lead wire terminal assembly, 23a-23
b is a lead wire terminal, 24a and 24b are insertion parts, 25a
- 25b indicates a protrusion. Episode 4
Claims (1)
線端子挿入用貫通孔が複数形成され、該貫通孔は内面に
は該パンケージ本体内の内部配線に接続された導体膜が
形成されていて、且つ、該パンケージ本体の主面および
裏面のどちらからでもリード線端子が挿入可能であって
、該貫通孔に複数の該リード線端子がそれぞれ挿入固着
されてなることを特徴とする半導体装置。 (2)前記複数のリード線端子は、前記パンケージ本体
とは別なる絶縁板で、相互に保持されていることを特徴
とする特許請求の範囲第(1)項記載の半導体装置。 (3)前記リード線端子は、前記半導体素子の搭載面と
同じ側に突出していることを特徴とする特許請求の範囲
第(11項又は第(2)項記載の半導体装置。 (4)半導体素子を搭載するパッケージ本体に、内面に
導体膜を有するリード線端子挿入用の貫通孔を複数個形
成する工程と、該パッケージ本体に該半導体素子の搭載
を行い封止する工程と、しかる後、複数のリード線端子
を該貫通孔に挿入固着する工程とを含むことを特徴とす
る半導体装置の製造方法。 (5)前記リード線端子を貫通孔に挿入固着する工程に
おいて、前記複数のリード線端子を予め絶縁板で相互に
保持しておき、それを前記貫通孔に一括挿入固着するこ
とを特徴とする特許請求の範囲第(4)項記載の半導体
装置の製造方法。[Claims] (11) A plurality of through holes for inserting lead wire terminals are formed in the package body on which the semiconductor element is mounted, and the through holes have a conductor film connected to the internal wiring in the pan cage body on the inner surface. The lead wire terminals can be inserted from either the main surface or the back surface of the pan cage main body, and a plurality of the lead wire terminals are inserted and fixed into the through holes, respectively. (2) The semiconductor device according to claim (1), wherein the plurality of lead wire terminals are mutually held by an insulating plate separate from the pancage body. (3) The semiconductor device according to claim 11 or (2), wherein the lead wire terminal protrudes on the same side as the mounting surface of the semiconductor element. (4) A step of forming a plurality of through holes for inserting lead wire terminals having a conductive film on the inner surface in a package body on which a semiconductor element is mounted, a step of mounting the semiconductor element in the package body and sealing it, and then a step of sealing the package body. (5) In the step of inserting and fixing a plurality of lead wire terminals into the through hole, the plurality of leads 4. The method of manufacturing a semiconductor device according to claim 4, wherein the wire terminals are mutually held in advance by insulating plates, and then inserted and fixed all at once into the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115566A JPS607752A (en) | 1983-06-27 | 1983-06-27 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115566A JPS607752A (en) | 1983-06-27 | 1983-06-27 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS607752A true JPS607752A (en) | 1985-01-16 |
| JPS6350865B2 JPS6350865B2 (en) | 1988-10-12 |
Family
ID=14665721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58115566A Granted JPS607752A (en) | 1983-06-27 | 1983-06-27 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607752A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62244156A (en) * | 1986-04-16 | 1987-10-24 | Ibiden Co Ltd | Surface mounting package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57141934A (en) * | 1981-02-27 | 1982-09-02 | Hitachi Ltd | Semiconductor device |
-
1983
- 1983-06-27 JP JP58115566A patent/JPS607752A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57141934A (en) * | 1981-02-27 | 1982-09-02 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62244156A (en) * | 1986-04-16 | 1987-10-24 | Ibiden Co Ltd | Surface mounting package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6350865B2 (en) | 1988-10-12 |
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