JPS607766A - Manufacture of solid-state image pick-up element - Google Patents

Abstract

PURPOSE:To obtain an interline transfer type CCD with an excellent pattern accuracy by a method wherein a one conductive type island domain is formed in a surface layer of a semiconductor substrate by an ion-implantation and the whole surface including the island domain is covered with a one conductive type epitaxial layer and a vertical transfer resistor part is formed in a part of the epitaxial layer corresponding to the island domain and a sensor part is formed in another part of the epitaxial layer. CONSTITUTION:An SiO2 film 22 is formed on a surface of a P type Si substrate 21 as a mask for an ion-implantation. A photoresist layer 23 of a prescribed pattern is formed and a part of the film 22 corresponding to a vertical transfer resitor part is removed. A P<+> type domain 24a is formed in the surface layer of the exposed part of the substrate 21 by an ion-implantaion. The layer 23 and the layer 22 are removed and a P type layer 31 is formed by an epitaxial growth and a part of the layer 31 corresponding to the domain 24a is converted into an N<-> type layer 26 as a resistor part. Another part of the layer 31 between zones where the domain 24a and the layer 26 are laminated is used as a sensor part 27. With this constitution, low energy ions can be used and the thickness of the mask can be made thin.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to solid-state image sensing devices, particularly interline transfer type CO
D relates to a method for manufacturing a solid-state image sensor.

BACKGROUND TECHNOLOGY AND PROBLEMS Solid-state imaging devices intended for application to color cameras have entered the practical stage and are under active development. Cameras using solid-state image sensors have problems in resolution, sensitivity, etc. when compared to tube-type cameras currently in practical use, and one area in particular that needs to be improved is the reduction of ζ smear. That is, in the interline transfer type COD solid-state image sensor, the sensor section (1
) when light (2) enters, and charges (4) photoelectrically converted deep in the semiconductor substrate (3) are taken into the buried channel layer (6) of the vertical transfer register section (5), smear occurs. arise. In the figure, (7) is an insulating film such as 5i02, (8) is a transparent sensor electrode, (9) is a transfer electrode, αO
) is a light shielding layer made of Aβ or the like. As a method for reducing this smear, as shown in FIG. There are ways to create a barrier to smear charges (4). In addition, there is one type of intrinsic getter, which forms recombination centers densely within the semiconductor substrate and removes smear charges within the substrate, and a method where the drive circuit is improved to eject the electric charge in the vertical transfer register section. etc. are also known.

By the way, in the smear reduction method using the configuration shown in FIG. The generated charge is diffused in the lateral direction, and the Smee r component increases. Therefore, it is necessary to transfer the impurity concentration of the island region under the sensor to be lower than the impurity concentration of the island region under the disk to form a barrier. On the other hand, for example, when a P-type island region is formed in a P-type semiconductor substrate, the impurity concentration of the P-type island region must be higher than the substrate concentration in order to act as a barrier against smear charges, and at least several A barrier of kT or more (Ic is Boltzmann's constant, T is absolute temperature) is required.

Normally, methods for forming P-type island regions include impurity concentration,
Ion implantation is used for depth control.

Figure 3 shows the conventional C method using island regions as a smear reduction method.
A method for manufacturing a CD solid-state image sensor will be described. In this example, first, an ion implantation mask (22) is formed on the main surface of a P-type silicon semiconductor substrate (21) using an acid such as 5i02 (see FIG. 1A). Only the portion of this oxide film (22) corresponding to the vertical transfer register portion is selectively etched using the resist layer (23) as a mask (31g1).
B-san! (Riri. The ion implantation conditions require the depth of the island region to be large, so the implantation energy is 300K.
It is necessary to make it more than eV. Therefore, oxidation 11Q (22
) alone is insufficient as a mask for ion implantation, so the bottom resist t-1m (23) used when patterning is also left. Next, boron ions are implanted to form the P-type first A! +
A region (24a) is formed (FIG. 3c). When ion implanting boron at 3001 (eν, L S S )
:! 4! According to theory, RP in silicon is 1.0002 μm.
, ΔRp = 0.143 μm, and in 5t02, Rp = 0.7536 μm, ΔRp −0,090
2, um, so S i0 is used as a mask for ion implantation.
A thickness of at least 1.08 μm or more is required.

Furthermore, when the implantation energy is increased, the oxide film (Si
Even two layers of o2) (22) and vol-resist layer (23) are insufficient. As the oxide film (22) becomes thicker, pattern accuracy decreases. Next, after this ion implantation, the photoresist layer (23) is peeled off, and heat treatment is performed for a long time at a temperature of 1100"C or more depending on the depth of the first island region (24a).
drive-in) (see diagram 3).

Next, CV D O) 5t0211 center (2
5) is deposited, and a portion of the Si02 film (25) corresponding to the region including the sensor section and the vertical transfer register section is selectively etched away (see FIG. 3E). Pattern accuracy in selective etching at this time is not required very much. Then, boron is ion-implanted to form a P-type f:A2
Forming the island region (24b) and heat treatment (drive-in)
(See Figure 3F). Next, the first island area (24a)
N of the vertical transfer register section in the island area (24) corresponding to
1 m (26) of - shaped buried channels are formed (see Figure 3G). Note that the second layer between the buried channel layers (26)
The island region (24b) becomes the sensor portion formation region (27).

In the subsequent steps, transfer electrodes are formed on the vertical transfer register section, sensor electrodes are formed, etc. in the same manner as in the CCD.
Necessary steps as a solid-state image sensor are performed.

However, the conventional manufacturing method, especially the P-shaped island region (24
) had the following problems. That is, high-energy ion implantation is required to form the first island region (24a), and therefore a thick oxide film is required as a mask for ion implantation, resulting in poor pattern accuracy.
Not from scratch. Especially in the case of high resolution, the pattern 'l'!
Since +1 ranges by 3 μm μm, it becomes difficult to form a pattern with high accuracy. Furthermore, if ion implantation with one possible energy is used, it is difficult to obtain an ion implantation mask that can withstand this. In other words, when the energy is 700KeV, 5i020
) Rp /'J< 1.3μm tear, 1.9μ
It requires a thickness of at least m, and it is difficult to use the two layers of the Sio2 film and the bottom resist layer as a mask.

In addition, since high energy ion implantation is used, the implantation is 4 tl.
The scratches become larger and crystal defects occur, which cannot be sufficiently recovered even with annealing treatment, causing image defects and an increase in dark current. In addition, in order to form the P-type 1J region deeply, it is necessary to perform heat treatment for a long time (at least 1100'C) after ion implantation, which may cause contamination from the furnace and damage to the silicon substrate. The impact of this cannot be ignored. At the same time, the increase in processing time is disadvantageous in terms of cost.Furthermore, there are problems not only with the problem of pattern formation, but also with the impurity concentration profile within the island region.Especially in the case of boron,
When the implantation energy is 500 KeV or less, the impurity concentration distribution in the P-type island region corresponding to the vertical transfer register section becomes a distribution that decreases directly toward the inside of the substrate at the surface of the substrate (distribution shown in Fig. 5). (n)). If an N-type buried channel layer is formed in the P-type island region in this state, since the surface concentration of the island region is high, it is necessary to increase the N-type impurity concentration, and the conditions for forming the buried channel layer are limited. become. Additionally, the position of the minimum potential of the buried channel layer moves toward the surface, making it more susceptible to surface traps.

OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a solid-state imaging device that improves the problems encountered in forming the above-mentioned island regions.

Summary of the Invention The present invention selectively forms an island region of one conductivity type on the main surface of a semiconductor substrate by ion implantation, and forms an island region of one conductivity type on the main surface of the substrate including the island region with an impurity concentration lower than that of the island region. A vertical transfer register portion is formed in a portion of this epitaxial layer corresponding to the island region, and a sensor portion is formed in another portion of the epitaxial layer.

In the bad method of this invention, since low-energy ion implantation can be used, the ion implantation mask becomes thinner, and the pattern M
'#Improvement of degree can be achieved. Further, heat treatment after ion implantation, impurity concentration distribution in the island region, etc. are improved.

Embodiment Hereinafter, an embodiment of the solid-state image sensing device according to the present invention will be described using FIG.

In the present invention, first, the 413th! ! As is usual with IA, for example, oxidation dust (22) to serve as a mask for ion implantation is deposited on the main surface of a P-type silicon semiconductor substrate (21) with an impurity concentration of about IQ'' cm-3. The oxide film (22) is formed by depositing a SiO+I model by thermal oxidation and 5i0211Q by CVD method.

Next, as shown in FIG. 4B, a portion of the oxidized nb (22) corresponding to the vertical transfer register portion is selectively etched away using the photoresist layer (23) as a mask.

Next, as shown in FIG. 4C, this photoresist layer (23
), for example, by implanting holons into the substrate (21).
A P-shaped first region (24a) having an impurity concentration of about lQlGcm-3 is formed on the main surface of the substrate. The ion implantation conditions at this time do not necessarily require high energy ion implantation, and may be low energy ion implantation of about 100 KeV, which is conventionally used.

Therefore, the film thickness of oxidation +1W (22) may be about 3000.

Next, after removing the photoresist layer (23), heat treatment is performed for a short time (10 to 20 minutes) at around 1000°C for the purpose of drive-in or annealing. This recovers the injection damage and also provides some drive-in (see Figure 4 (■)).

Next, as shown in FIG. 4E, the oxidized (oxidized) return (23) is completely removed and a P area corresponding to the second island region is formed on the main surface of the base (21).
A shaped epitaxial M (31) is grown.

This epitaxial condition has an impurity concentration of 101' to 10
The material may be about 15cIn-3 and the thickness may be about 1 μm. With the current epitaxial technology, it is possible to guarantee a variation within 110% in a thickness of 1 μm in epitaxial growth using 5i14, so there is no problem in controlling the thickness. And 102
Since the process is carried out at a temperature of around 0°C, the occurrence of defects can be sufficiently controlled. Further, the impurity concentration of the first island region (24a) is 1016
Since it is about cm-3, there is no auto-doping and the concentration profile in the epitaxial JfA (31) can be accurately controlled.

Next, as shown in FIG. 4E, an epitaxial layer <31) is formed.
(7) Form an N-type buried channel layer (26) of the vertical transfer register section in a portion corresponding to the first island territory (24a). Further, a portion of the epitaxial layer (31) corresponding to between the buried channel layers (26) is used as a sensor portion formation region (27), and a sensor portion is formed therebetween. The subsequent steps are to form a channel stop region and an overflow drain region (not necessary in the case of a vertical overflow drain structure) in the same way as for energization, and to form a transfer electrode on the vertical transfer register section via an insulating film, or Interline transfer type COD by forming sensor electrodes etc.
Configure a solid-state image sensor.

According to this manufacturing method, in the island region (24) corresponding to the vertical transfer register section, the first island region (24) on the substrate side
The impurity concentration of a) can be arbitrarily controlled by ion implantation, and the impurity concentration of the part (a) where the buried channel layer (26) is formed can be controlled arbitrarily by ion implantation.
The impurity concentration of the so-called second island region) is epitaxially [(3
1) can be controlled separately. Therefore, an impurity concentration distribution (1) as shown in FIG. 6 is obtained in the P-type island region (24). Incidentally, FIG. 5 shows the impurity concentration distribution (n) of the conventional P-type island region (24) produced by the manufacturing method shown in FIG.

When forming the buried channel layer of the vertical transfer register section, if the basic concentration is high, it is necessary to increase the surface concentration of one example of the buried channel, making it difficult to form a buried channel structure. As the concentration of the buried layer increases, the minimum
Since the position of the potential is closer to the fundamental surface, it is closer to surface channel behavior. Therefore, the impurity concentration in the island region of the buried channel forming portion needs to be low. On the other hand, in order to prevent charges caused by light incident into the substrate from the sensor section from entering the vertical transfer register section, it is necessary that the impurity concentration of the island region under the buried channel Yi is higher than that of the substrate. In this manufacturing method, as shown in the impurity concentration distribution (1) in Figure 6, the buried channel forming part of the island region has a low concentration, and the deeper part has a higher concentration than the base, so smear prevention is ensured. At the same time, a compact buried channel operation is maintained.

Further, in this manufacturing method, high energy ion implantation as in the conventional method is not required as ion implantation for forming the first island region (24a). For this reason, the oxide film (22) serving as an ion implantation mask can be made thin, and pattern accuracy during mask formation is improved. This has a pattern width of 3
It is suitable for forming a solid-state image sensor with a Nishiwaki image resolution of 0 μm or more. Furthermore, since the buried channel layer of the vertical transfer register section is formed in the epitaxial layer (31), there is no implantation damage or crystal defects caused by conventional ion implantation, and image defects, increase in dark current, etc. can be avoided. Further, since there is no need to make the first island region (24a) deep, the heat treatment after ion implantation can be performed at a lower temperature and in a shorter time. Therefore, contamination from the furnace and adverse effects on the semiconductor substrate are eliminated, and
It also shortens process processing time.

Note that in the method of forming a P-type island region on a P-type semiconductor substrate, the concentration of the sensor portion and the concentration of the substrate may be the same. In addition, in this manufacturing method, as a method of creating a mark for pattern alignment after the formation of the first island region (24a), a selective epitaxy method can be used, leaving a 5i02 reflection only in the mark part.

In the second section, a case has been described in which a P-type island region is formed in a P-type semiconductor substrate, but as shown in FIG. 7, a P-type island region, that is, a first island region (24a)
The present invention can also be applied to a configuration in which an epitaxial layer (31) is formed. Furthermore, it can also be applied to a configuration in which the conductivity types are reversed.

Effects of the Invention According to the present invention described above, an island region of one conductivity type is selectively formed on the main surface of a semiconductor substrate by ion implantation, and an epitaxial layer of one conductivity type is formed on the island region with an impurity concentration lower than that of the island region. , low-energy ion implantation can be used for ion implantation. For this reason, the oxide layer used as the mask for ion implantation can be made thinner, and the pattern accuracy when forming the mask is improved. Further, since the high concentration island region formed by ion implantation is located at a substantially deep position, heat treatment after ion implantation can be performed at a low temperature and in a short time. Furthermore, since the vertical transfer register section is formed in a portion corresponding to the island region of the epitaxial fence, the concentration of the vertical transfer register section can be controlled.

As described above, the present invention can improve the reliability of a solid-state imaging device using the υJ region as a smear reduction method, and can also achieve high resolution.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a solid-state image sensor used to explain the present invention, FIG. 3 is a cross-sectional view showing an example of a conventional method for tearing a solid-state image sensor, and FIG. 4 is a cross-sectional view of the process according to the present invention. 1 and 5 are cross-sectional views of the process order showing an example of the manufacturing method of a solid-state imaging cord, and FIG. 5 is an impurity concentration distribution diagram of the island region according to the conventional manufacturing method, and FIG. FIG. 7 is a 1lli side view showing another embodiment of the present invention. (21) is the semiconductor substrate, and <24a) is the - conductivity type first
111 region, (26) is a buried channel layer of the vertical transfer register section, and (31) is a − conductivity type epitaxial layer. -3 Figure 22 Figure 3 Figure 4 - Figure Rough Figure 9 Figure 5 Figure 6 Figure 1

Claims (1)

[Claims] An island region of one conductivity type is selectively formed on the main surface of a semiconductor substrate by ion implantation, and an epitaxial layer of one conductivity type with a lower impurity concentration than the island region is formed on the main surface of the substrate including the island region. . A method for manufacturing a solid-state imaging device, characterized in that a vertical transfer register section is formed in a portion of the epitaxial layer corresponding to the island region, and a sensor section is formed in another portion of the epitaxial layer.