JPS6077781A - Pinball machine - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention secures a predetermined winning right by the entry of a pachinko ball into a predetermined winning opening, and when the winning right is secured, the pachinko ball enters the predetermined winning opening. When a pachinko ball flies into a different winning hole, the prescribed winning right is exercised, and when a pachinko ball flies into a winning hole different from the predetermined winning hole without securing the prescribed winning right. The present invention relates to a pachinko machine that exercises rights that have a lower probability of winning than the predetermined winning rights.

(Prior art) Haf7ko4i [id, When a pachinko ball flies into a predetermined winning hole, there is a device that increases the winning probability of a winning device.

However, this German pachinko machine only increases the probability of winning by a predetermined amount each time a pachinko ball enters the winning hole, so it is difficult for players living in modern times to play pachinko to play pachinko. As the game progresses, it becomes monotonous, and the player's ability to play V-1; Z-hoko tends to decline.

(Object of the Invention) The present invention was made in view of the above-mentioned circumstances, and its purpose is to provide a pachinko machine that is rich in game variety and stimulates the player's desire to play.

(Structure of the Invention) In order to achieve such an object, the present invention includes a solenoid that increases the probability of winning, and a first solenoid that is turned on when a pachinko ball enters a winning opening for securing rights. The right 1j stock guarantee circuit is set to the winning probability increasing state driving preparation state, and the guarantee circuit is in the on state and the pachinko ball is placed in a winning opening used for right line that is different from the winning opening for securing the right. When the solenoid jumps in and is turned on, the solenoid is driven so as to be in the first winning probability increasing state, and the Izeo U securing circuit is in the on state and the pachinko When the ball flies in and is turned on, the solenoid is switched to a second state with a lower probability than the first winning probability increasing state.
This configuration includes a rights exercise circuit that drives the player to increase the probability of winning a prize.

From the above-mentioned configuration, even if a pachinko ball flies into the 4-way winning slot, the winning probability can be increased depending on whether the winning position is secured, and the player can play pachinko with a wide variety of games. In addition to being able to enjoy the game, the player's desire to play is increased because the player can obtain the above-mentioned prize probability state based on his/her skill.

(Example) Embodiments of the present invention will be described below based on the drawings.

1 to 4, 1 is a winning device according to the present invention, and this winning device 1 includes a first winning device 2 and a second winning device 3.
It consists of this 1st. A second person ((The devices 2 and 3 are attached to the game board surface 4 in a vertical relationship.

The first prize device a2 has a casing 5 made of plastic.
The upper portion thereof is provided with a large entry shell opening 6, the left and right diving winning lowers 8, and the lower portion thereof is provided with left and right diving winning openings 9, 10. The sky prize opening 6, left and right sky shoulder diving prizes 1:17, 8 are normal winning ball detection mechanisms (
When a pachinko ball enters the mouths 6, 7, and 8 of both players, the winning ball detection mechanism pays out a ball of a predetermined value.

Left and right 2) The exit openings 9 and 10 open downward, and when a pachinko ball enters the left and right entry openings 9 and 10, the pachinko ball is sent to the second winning device. 6
You will be guided towards 3.

The center of the casing 5 of the first prize-winning device 2, that is, the top prize bottom 6. A prize opening 11 is opened between the left and right upper openings 8 and the left and right openings 9 and 10. [A center gate 12 is supported at both ends of the edge. This center gate 12 has a guide plate section 12. and 1l (ll plate parts 12b, 12b. Guide machine part 1
2a is pivoted at both ends of its lower end to the opening edge of the winning slot 11, and the upper end of the guide plate 12a is connected to the game board surface 4.
The winning opening 11 is opened and closed using both ends of the lower end of the guide plate part 12a as fulcrums in the direction of approaching and separating from the guide plate part 12a. (110 board capitals 12b are erected at both ends of the guide plate portion 12a, and the weight of the side plate portions 12b, 12b causes the guide plate portion 12a to
is always biased in the open direction. That is, this side plate part 12b has a layered shape, and one end edge thereof is fixed to both ends of the guide plate part 12a, and the other end edge part extends in a direction away from the front surface of the casing 5. Therefore, the guide plate portion 12a opens until the other end edge of each side plate portion 12b comes into contact with the front surface of the casing 5, and the angle formed between the other end edge and one end edge of each side plate portion 12b. determines whether the guide plate portion 12a is to be opened or hidden. Then, each side plate portion 12b
The other end edge extends at the left and right diving prize openings 9, 104 when the other end edge comes into contact with the front surface of the casing 5, and at that time, each side plate portion 12b and the front surface of the casing 5 are erected. Standing up &16.16 means left and right diving entrance ν,
Passage 13a that increases the probability of a batinko ball flying into 10
, 15a are formed. And this center gate 12
As shown in FIG. A count switch 16 for counting the number of pachinko balls is built-in.

The second human body device 3 has a casing 17 made of plastic.
The upper part is formed with a receiving part 1Ilt1 which receives the penis balls that have entered the above-mentioned pressure right entry ports 9 and 10.
8 is provided. The saucer 18 Vi casing 17
It is connected to the front by a wide dick ball passage 19, so that the dick ball 1d received in the receiving part 118 rolls forward through the dick ball passage 19. It has become. On the front of the 1st floor of the casing, there is a
A partition portion 20°2 is provided below the opening of the tenco ball passage 19.
1 is standing upright, and between this partition part 20 and 21 is a piece of bamboo 1.
It is said that the number of people to secure the right is χ, and the winning opening for securing this right is 22.
has a built-in rights securing switch 26. On both sides of the winning slot 22 for securing rights, normal openings 24 and 25 from which a predetermined number of winning balls are paid out are provided. ,
A rights securing display lamp 26 is provided.

On the front of the casing 17, there is a prize opening 22 for securing rights. Winning slots 27.28 and 27.28 are available on both sides of winning slots 24.25 and 27.28.
27.2.
8 is provided with a power exercise switch 29, respectively. 30.51 is a plaque, and 52 is a right exercise indicator lamp.

Figure 4 shows the control circuit for the solenoid 15,
, 34. j5 is a flip-flop circuit, Otsu6 is a clock oscillation circuit, 37 is a 12-bit binary power counter circuit iJ,
38, 39, 40 are reset circuits, 41 is a lamp display blinking circuit, 42 is a solenoid drive circuit, 43 is a right reservation display lamp drive circuit, 44 is a right exercise display lamp drive circuit, 45 is a 10 count storage circuit, 46 is '
47 is a sound amplification circuit. Of these, the flip-flop circuit 63 and the 7-lip 70-tub circuit 64 roughly constitute the rights securing circuit, the flip-flop circuit 65, the reset circuit '58, 59, 40, the clock oscillation circuit 66, the 12-bit binary power counter circuit 37, and the The solenoid drive circuit 42 generally constitutes a rights enforcement circuit.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 33 has an input terminal C, a source potential terminal 1], a ground terminal S, and an output terminal Q.

Q and a reset terminal R. The input terminal C is connected to the source voltage VCC and the rights securing switch 23 via the Nant gate 49, and the source voltage Vcc is set to the high potential side. As shown in the figure, in the open state, the output ψ;
is outputting L, and when the M protection switch 26 is closed, one clock is input to the input terminal C, and H is output to the output terminal Q. Qke is not used here.

The flip-flop circuit 34 has an input terminal C, a ground terminal S, output terminals Q, Q, and a reset terminal R. The output from the output terminal Q of the Noritsubu flop circuit 63 is input to the input terminal I), and the input terminal C is connected to the 4Tb interest-bearing switch 29 via the AND circuit 50 and the Nant gate 51. When the control switch 29 is in the open state as shown in FIG.
The AND circuit 50 outputs L, and when the right exercise switch 29 is closed due to the landing of a pachinko ball, the AND circuit 50 outputs H. The output of this AND circuit 50 is passed through an OR circuit 52 to a flip-flop circuit 63.
When the AND circuit 50 outputs an H level, the Noritsubu flop circuit 33 is reset and its output terminal Q becomes an L state. One clock is input to the input terminal C of the flip-flop circuit 64 when the Y81'' exercise switch 29 is closed. When the terminal DICL is inputted, an L is outputted from -i, and when an H is inputted to that input terminal, an H is outputted. The output terminal point outputs an output signal opposite to that of the output terminal Q.

The flip-flop circuit 35 consists of two NOR circuits 53 and 54.
The output of the AND circuit 50 is input to one input terminal of the NOR circuit 56, the output of the NOR circuit 56 is input to the input terminal of the NOR circuit 54, and the output of the NOR circuit 54 is input to the input terminal of the NOR circuit 56. The input terminal of the circuit 53 is inputted, and the output of an OR circuit 55, which will be described later, is inputted to the input terminal of the NOR circuit 54. In this flip-flop circuit 35, L is input to the NOR circuit 53, and the NOR circuit 54
When H is input to , it outputs L and inputs H to NOR circuit 53
is input and the NOR circuit 54VCL is input, H
It has a function of outputting the previous state when L is input to both NOR circuits 53 and 54.

The 12-bit binary power counter circuit 37 has an input terminal C, output terminals Q, -Q, □, and a reset terminal R. The input terminal C is connected to a clock oscillation circuit 36 which generates a lock signal as shown in FIG. 5, and each output terminal Q, -Q+2 is configured to generate a rectangular signal as shown in FIG. ing. The output terminal Q has a period twice that of the clock signal, and has a function of outputting when the first clock signal is input.

The output terminal Q2 has a period four times as long as the period of the clock signal, and has a function of outputting when the second scan clock signal is input. Output terminal Q, Id.

It has a period eight times the period of the clock signal, and has a function of outputting when the fourth clock signal is input.

The output terminal Q4 has a cycle that is 16 times the cycle of the clock signal, and has a function of outputting when the eighth clock signal is input. The output terminal q has a period 32 times the period of the clock signal, and outputs when the 16th clock signal is input. The output terminal Q6 has a cycle that is 64 times the cycle of the clock signal, and outputs when the 32nd clock signal is input. The output terminal Q has a period 128 times the period of the clock signal, and outputs when the 64th clock signal is input manually. The output terminal Qa ld has a period 256 times the period of the clock signal, and outputs when the 128th clock signal is input. The output terminal Q9 is 512 times the period of the clock signal.
It has twice the period and is output when the 256th clock signal is input. Output terminal Q. has a cycle that is 1024 times the cycle of the clock signal, and is output when the 512th full clock signal is manually input. Output terminal Q++
has a revolution that is 2048 times the period of the clock signal,
It is output when the 128th clock signal is input. The output terminal Q+2 is 4096 times the period of the clock signal.
It has twice the period and outputs when the 2048th odd clock signal is input.

The reset circuit 58 consists of an AND circuit 56, which includes a 12-bit binary power counter circuit 57.
The outputs of output terminals Q, , Q, are input. The output of this AND circuit 56 is input to an OR circuit 55. In addition to this, the output from the output terminal Q of the flip-flop circuit 34 is input to the OR circuit 55, and the output from the output terminal reset circuit 57 is also input. , as described above, is input to the input terminal of the NOR circuit 54 as a component of the flip-flop circuit 35.

Here, a wake-up reset circuit 57L is provided.

42 solenoid drive circuits, 58° OR circuit, 5 resistors
9. It consists of a transistor 60, etc., and each of these components 5
8, 59, and 60 to the solenoid 15. The OR circuit 58 includes a flip-flop circuit 35.
and the output terminal of the 12-bit binary power counter igl path 67. 7 pieces of output are input.

The reset circuit 39 includes a NOR circuit 61 and an It has a code circuit 62 and an OR circuit 63.

The output of the flip-flop circuit 55 and the output from the output terminal Q of the flip-flop circuit 34 are input to the NOR circuit 61 . The AND circuit 62 receives the output of the NOR circuit 61 and the outputs from the output terminals of the 12-bit binary power counter circuit 57. In the OR circuit 63,
The output of the AND circuit 62 and the output of the AND circuit 50 are input, and the output of the OR circuit 63 is input to the reset terminal R of the 12-bit binary power counter circuit 67. When the right exercise switch 29 is in the open state, that is, when the AND circuit 50 is outputting L and the NOR circuit 61 is outputting H, 12
The output signal from the output terminal Q6 of the bit binary power counter circuit 37 is passed through an AND circuit 62 and an OR circuit 63 to
The signal is input to the reset terminal R of the 2-bit binary power counter circuit 67, and the output signal causes the +i 12-bit binary counter circuit 37 to be reset and released repeatedly.

More specifically, the output signal from the output terminal q is L.
state, the 12-bit binary power counter circuit 37
The reset is released, and when the output signal becomes H state (at the first rise of), the 12-bit binary force counter circuit 37 is reset.The 12-bit binary force counter circuit 37 is reset. Then, the output terminals Q1 to QI2 become L state, so L is output from the OR circuit 63, the reset of the 12-bit binary power counter circuit 57 is released, and from the time of this reset release, a new 12 bits are output. The output terminals Q1 to QI2 of the bit binary force counter circuit 37 start outputting each rectangular signal. Therefore, the output terminals Q and -Q+2 of this 12-bit binary force counter circuit 57 are in the L state. If L is being output from the NOR circuit 61, L will be output from the OR circuit 63, and the 12-bit binary force counter circuit 37 will be in the reset release state. and each output terminal Q, -
Q, , output rectangular signals shown in FIGS. 5 and 6, respectively.

When the right exercise switch 29 is closed, the OR circuit 63 outputs H, and the 12-bit binary power counter circuit 37 is reset regardless of the output signal from the AND circuit 62. . As a result, 12
The pit counter circuit 57 determines the start time of operation for starting the first or second winning probability increasing state, that is, the reference time.

The reset circuit 40 includes an AND circuit 64, an inverter element 65, and a NOR gate 66. The AND circuit 64 receives the output of the output terminal Qo + Q10 of the 12-piston ζ initial force counter circuit 57. The output terminal (f, 1) of the AND circuit 64 is connected to one input terminal of a NOR gate 66 via an inverter element 65, and the other input terminal of the NOR gate 66 is grounded via a capacitor. The ground side of is in the L state.

The output of the NOR gate 66 is input to an OR circuit 67. The OR circuit 57 also receives an output from the power supply reset circuit 57 and an output from an AND circuit 68 (to be described later), and the output from the OR circuit 67 is input to the reset terminal of the flip-flop circuit 34. There is. When the OR circuit 67 outputs a high level, the flip-flop circuit 54 is reset, and the output from its output terminal Q becomes L, and the output from its output terminal q becomes H.

The lamp display blinking circuit 41 has AND circuits 69 and 70. The AND circuit 69 has an output terminal q of the 12-bit binary power counter circuit 37.

The AND circuit 70 receives the output from the output terminal Q of the flip-flop circuit 34 and the output terminal Q of the 12-bit binary power counter circuit 37.
The output from 4 is input.

The right securing display lamp drive circuit 43 is an AND circuit 7
1, a resistor 72, and a transistor 73.

The output from the output terminal Q of the flip-flop circuit 33 and the output from the AND circuit 69 are input to the AND circuit 71.
and the right securing indicator lamp 26 via the transistor 73.
is input.

The right exercise indicator lamp drive circuit 44 is an OR circuit 74
, a resistor 75, and a transistor 76. The output from the flip-flop circuit 35 and the output from the AND circuit 70 are input to the OR circuit 74 .
The output Id of 4 is inputted to the amplifier 52 indicating the right exercise H via the low resistance 5 and the transistor 76.

The 10-count storage circuit 45 includes a 4-bit binary counter circuit 77 and an AND circuit 6B. The 4-bit binary counter circuit 77 has a reset terminal R, an input terminal C, a power supply potential terminal CE, an output terminal Q, ~Q4
have. The output from the output terminal Q of the flip-flop circuit 64 is input to this reset terminal R, and the output terminal 04 to which this reset terminal RICH is input is input.
The bit binary counter circuit 77 is reset and each output terminal QI"Q4 goes into the L state. The input terminal C of this 4-bit binary counter circuit 77 is connected to the input terminal of a Nant gate 78, and the Nant gate 78 The count switch 16 is connected to the input terminal of the gate 78 .

This count switch 16 is closed every time a pachinko ball wins and inputs one clock to the input terminal C of the 4-bit binary counter circuit 77, and when L is input to the reset terminal R, it corresponds to the number of clocks. output terminals Q, -Q
, H is output from. That is, initially, the output terminal Q
, ~Q4 all output L, and when one clock is input, only output terminal Q outputs H, and when two clocks are input, only output terminal Q2 outputs H. output, and when three clocks are input, output terminals Q1 and Q2
outputs H, and when 4 clocks are input, only output terminal Q3 outputs Hf, and when 5 clocks are input, output terminals Q and Q output H, When 6 clocks are input, output terminals Q2 and Q output H, and when 7 clocks are input, output terminals Q and Q output
.

and Q output H, and when 8 clocks are input, only output terminal Q4 outputs H, and when 9 clocks are input, output terminals Q1 and Q4 output ■]. Output and 1
When a clock of 0 is input, output terminals Q2 and Q4 output 11. The output from the output terminal Q2.Q of the l''t4t4 pitt nolly counter circuit 77 is input to the AND circuit 68, and the output from the AND circuit 68 is inputted to the OR circuit 67. When 10 clocks are input to the input terminal C of the bit counter circuit 77, output terminals q, Q, and 75;H are output, so the AND circuit 68 outputs H, and the OR circuit 67 outputs the H output. In response, the reset terminal Ru of the flip-flop circuit 34 becomes H and is set.

The '1u consonant generation circuit 46 includes the output of the NOR circuit 61 and the output terminal Q of the inary counter circuit 67.
, and the electronic sound generation circuit 46.
The output from is input to the audio amplification circuit 47. 78
is a speaker.

Next, the effects will be explained separately for each case.

(1) Rights exercise switch 29. Rights securing switch 23,
All of the count switches 16 are open, the output terminal Q of the flip-flop circuit 33 outputs L, and the output terminals Q1 to 4 of the 4-bit biner IJ-counter circuit 77
When Q4 is outputting L.

When the voltage vCC is turned on, the 12-bit binary force counter circuit 37 starts operating in the reset release state, and since the right exercise switch 29 is at the H level in the open state, the AND circuit wJ50 outputs the L level. On the other hand, since the output from the output terminal Q of the flip-flop circuit 53 is input to the input terminal of the flip-flop circuit 54, the output terminal Q of the color flip-flop circuit 54 outputs L. The output terminals IQ, , Q6 of the 12-bit binary power counter circuit 37 output signals (the output terminal Q6 outputs L).
47%) is output, and the two river force signals are passed through an AND circuit 56 and an OR circuit 55 to a flip-flop circuit 55.
is input to the NOR circuit 54 as a component of
At this time, the L output from the AND circuit 50 is input to the NOR circuit 53 as a component of the flip-flop circuit 65, and since the signal input to the NOR circuit 54 is L, the flip-flop circuit 55 is always Outputs L. The NOR circuit 61 includes the output from the flip-flop circuit 35 and the output terminal Q of the flip-flop circuit 34.
The output from is input, and the NOR circuit 61fd,
Therefore, H is output.

The AND circuit 62 has the H output from the NOR circuit 61 and the 12
The output signal from the output terminal Q6 of the bit binary power counter circuit 37 is input, and the AND circuit 62 outputs the same output signal as the output signal from the output terminal q. OR times 1% 631fC is input with the L output from the AND circuit 50 and the output signal from the AND circuit 62, and the OR circuit 63 outputs the same output signal as the output signal from the AND circuit 62, and its output 1 The signal is input to the reset terminal R of the 12-bit binary power counter circuit 57. Therefore, as a result, the 12-bit binary power counter circuit 37
The output signal from the output terminal Q6 is input to the reset terminal R, and the 12-bit binary force counter circuit 37 is reset in accordance with the output signal, that is, when the output signal becomes H state. and the output signal is L
When the state is reached, the reset is released. For this reason,
Each output terminal of the 12-bit binary force counter circuit 67 starts outputting from the beginning every time the reset is released, and the output terminals Q, to Q+2 of the 12-bit binary force counter circuit 37 output a rectangular signal. It is in the L state without any problems.

Therefore, the OR circuit 58 receives the coL output from the output terminal Q7 of the 12-bit binary power counter circuit 67 and the L output from the flip-flop circuit 55.
OR circuit 58 is outputting IJ. This OR circuit 58
The lunoid 15 is driven by the L output from tl, which is not in the fall 1 store, and the center gate is in the closed state.

The AND circuit 71 receives the output from the output terminal Q of the flip-flop circuit 53, and therefore, the AND circuit 71 outputs L. L from this AND circuit 71
Due to the output, the "Yu 1" reservation indicator lamp 26 is turned off.

The AND circuit 70K receives the L output from the output terminal Q of the flip-flop circuit 64, and
outputs L. The L output from the flip-flop circuit 35 and the L output from the AND circuit 70 are input to the OR circuit 74, and the OR circuit 74 outputs L. The right exercise indicator lamp 62 is turned off by the L output of the OR circuit 74.

(iil The output terminal Q of the flip-flop circuit 53 is L
is being output, and the I-butsuri-gyo-1-history switch 29 is closed.

When a pachinko ball enters the winning opening 27, the pachinko ball temporarily closes the play switch 29, and accordingly, an H signal is output from the AND circuit 5oHI. The H output from the AND circuit 50 is input to the OR circuit 63, and the OR circuit 63 is connected to the AND circuit 62.
Outputs H regardless of the output signal from. The H output is input to the reset terminal R of the 12-bit binary power counter circuit 67, and is applied to the 12-bit binary power counter circuit 57. This causes solenoid 15
A reference time (start reference time) for driving will be determined. That is, with the closing of the first right exercise switch 29, the H output from the AND circuit 50 is input to the NOR circuit 56, while the 12-bit binary power counter circuit 37 is reset as described above. At this time, the OR circuit 55 is manually inputting L to the NOR circuit 54. Therefore, the flip-flop circuit 35 outputs H, and the OR circuit 58 receives the H output and the L output from the output terminal Q7 of the 12-hit binary power counter circuit 37, which is in the reset state. That will happen. As a result, the OR circuit 58 starts outputting H, and the driving of the solenoid 15 starts.

The pachinko ball leaves the hit switch 29 and Ichisen F.
When the 1st row 1 history switch 29 returns to the open state, the AND circuit 50 outputs L from H;
The output is input to an OR circuit 65. Upon receiving the input, the OR circuit 63 inputs the L output to the reset terminal R of the 12-bit binary power counter circuit 7, and releases the reset state of the 12-bit binary power counter circuit 37.

12-bit binary power counter circuit 37 reset state! b
When is released, its output terminal Q4゜Q, is as shown in Fig. 5.
A rectangular signal shown in FIG. 7 is output, and the output is input to an AND circuit 56.

In response to this, the AND circuit 56 outputs a rectangular signal shown in FIG. 7, and its output is input to the OR circuit 55. At this time, all other input signals input to the OR circuit 55 are L, so the OR circuit 55 outputs the same rectangular signal as the AND circuit 56, and the output signal is sent to the NOR circuit 54. is input. At this time, the benefit exercise switch 29
With the return to the open state, L is input to the NOR circuit 56.

Therefore, the flip-flop circuit 55 is the OR circuit 55
Since the input of the rectangular signal starts from , only L is input for 0.5 seconds, so the flip-flop circuit 65
During that time, outputs the previous state 1, that is, H. 1
During this time, the output signal from the output terminal Q7 of the 2-bit binary force counter circuit 57 is outputting L again, so the OR circuit 58 continues to output H, and the driving of the solenoid 15 continues.

At this time, H from flip-flop times 11!2555
The output is also input to the NOR circuit 61. The Noah circuit 61 is
It receives the H output and the L output from the output terminal Q of the 7 lip-flop 1!2 circuit 64 and outputs L<, and the L output is input to the AND circuit 62. The AND circuit 62 L is output, the L output is input to the OR circuit 63, and the OR circuit 6
3 inputs the L output to the reset terminal R of the 12-bit binary power counter circuit 67.

Therefore, the IHji outputting H from the free-laugh 0 flop circuit 35 and the 12-bit binary output counter circuit 57
has been reset.

3 (2 ) Then, the rectangular signal inputs the 1] state to the NOR circuit 54, and since L is input to the NOR circuit 53, it outputs the flip-flop circuit 651dL.

Therefore, while L is input to the NOR circuit 53,
Thereafter, even if the output signal from the OR circuit 55 input to the NOR circuit 54 changes, the flip-flop circuit 35 continues to output L.

The L output from the flip-flop circuit 55 is sent to the NOR circuit 6.
1, and the NOR circuit 61 outputs H. Therefore, the H output of the AND circuit 62 and the rectangular signal from the output terminal q of the 12-bit binary power counter circuit 57 are input, and as mentioned in section a. (1) above, the 12-bit binary The force counter circuit 37 is repeatedly reset and released according to the output signal from the output terminal Q6, and the output terminals Q7 to Q, 2 of the B12-bit binary counter circuit 57 become L-shaped +7g. Therefore, the L output from the flip-flop circuit 65 and the L output from the output terminal Q7 of the 12-bit binary power counter circuit 37 are input to the OR circuit 58, and the OR circuit 58 outputs [L]. This L output causes the solenoid 15 to stop driving and the center gate 12 to be in the closed state. That is, as shown in FIG. 7, the solenoid 15 is driven once for 5 seconds, the center gate 12 is opened and closed once, and the second winning probability increasing state is activated.

Since L is still output from the output terminal Q of the flip-flop circuit 33 to the AND circuit 71, the AND circuit 71 outputs L, and the right reservation indicator lamp 26 is turned off. There is.

The L output from the output terminal Q of the flip-flop circuit 34 is input to the AND circuit 70.
outputs L, and inputs the L output to the OR circuit 74. Additionally, the OR circuit 74 includes a flip-flop circuit 3.
Since the output signal from 5 is input, the OR circuit 74
The same signal as the output signal from the flip-flop circuit 35 is outputted, and the output signal from the flip-flop circuit 35 is
2 is turned on when the output (, ff) is in the 11 state, and is turned off when the output signal 4 is in the L state. In other words, the right row '+ERi lamp 62 is activated together with the solenoid 15 when the solenoid 15 is driven. Lights up while

(i)i) The output terminals Q and -Q of the 4-bint pinary-count circuit 77 are in the L state, and first, the rights securing switch 26 is closed, and then the its rights exercise switch 29 is closed. case.

When a pachinko ball enters the left and right diving prize openings 9.10, the pachinko ball is dropped into the receiver 111118 of the second player's prize device O through the pachinko ball path 19 from the receiver 18 to the second player's prize device. Guided to the front of ρ3. When the pachinko ball falls from the opening of the pachinko ball passage 19 and enters the prize opening 24.25, the prize ball of the L5i Articles of Incorporation is paid out and placed in the winning opening 22 for securing rights as usual. If the object falls and enters the object, the rights securing switch 25 is closed.

When the rights securing switch 23 is closed, one clock is input to the input terminal C of the flip-flop circuit 56, and the output terminal Q thereof outputs an H level. Its H output is AND circuit 7
1 and is also input to the input terminal of the flip-flop circuit 34 and stored in the flip-flop circuit 64. The AND circuit 69 receives the rectangular signals from the output terminals Q, , Q, of the 12-bit binary power counter circuit 67, and receives both of the rectangular signals and outputs an output signal. The output signal is input to an AND circuit 71'. Therefore, the AND circuit 71 outputs the same output signal as the AND circuit 69 to the separation ensuring display lamp 26.
As a result, the profit securing table failure lamp 26 repeatedly blinks. By blinking the 1st reservation indicator lamp 26, the player knows that the right to prepare for the 1st personnel probability increased state, that is, the right to the 10th entry 1 (probability increased state) has been secured. .

Since the output from the flip-flop circuit 35 and the L output from the AND circuit 70 are input to the OR circuit 74 without change, the right AIJ flight display lamp 62 is turned off.

Accordingly, as shown in WJ (4), the right-bearing servant 14
When a pachinko ball flies into the mouth 27, the security switch 2
9 is temporarily closed, and one clock is manually applied to the input terminal C of the flip-flop circuit 34. As a result, its output terminal Q is input to the input terminal C of the flip-flop circuit 34.
outputs the H state stored in the memory. Therefore, the NOR circuit 61 outputs L, the AND circuit 62 outputs L, and only L is input to the OR circuit 63. On the other hand, I'1J5y, KLl) of the 1st history switch 29, and the AND circuit 50
outputs H from L, and the H output is input to the OR circuit 66. As a result, the OR circuit 63 outputs H, the 12-bit binary force counter circuit 67 is reset, and the reference time for driving the solenoid 15 is determined.

When the pachinko ball leaves the right exercise switch 29 and the right exercise switch 29 returns to the open state, the AND circuit 5
0 means K to output L from H, and the L output is manually input to the ID OR circuit 65. The OR circuit 66 outputs L based on the L output from the AND circuit 62 and this L output,
The reset of the 12-hit binary force counter circuit 57 continues to be released.

12 Hints With the release of the reset of the binary force counter circuit 57, the rectangular signals shown in FIGS. 5 and 6 are output from its output terminals Q, . . . The output signal is inputted to the OR circuit 55 via the AND circuit 56. However, this OR circuit is inputted with the striking output from the output terminal Q of the flip-flop circuit 54, the OR circuit 55 outputs H, and this striking output is input into the NOR circuit 54. At this time, since the right exercise switch 29 has returned from the closed state to the open state, the AND circuit 50 inputs L to the NOR circuit 53, and therefore the flip-flop circuit 35 outputs L. The hitting force is input to the OR circuit 58. A rectangular signal from the output terminal Q7 of the 12-bit binary power counter circuit is input to the OR circuit 58, and the OR circuit 58 outputs the rectangular signal shown in FIG. Therefore, the solenoid is driven at 0.8 second intervals, and the center gate 1
2 turns around to open and close.

A rectangular signal from the output terminals Q, , Q, of the 12-bit binary power counter circuit 67 is input to the AND circuit 64, and the AND circuit 64 outputs the rectangular signal shown in FIG. This output signal is input to a NOR gate 66 via an inverter element 65, and the NOR gate 66 outputs an inverted rectangular signal of the AND circuit 64, and the output signal from the NOR gate 66 is input to an OR circuit 67. At this time, the power supply reset circuit 57 and the AND circuit 68
outputs L, and this striking power is input to the OR circuit 67. Therefore, the OR circuit 67 outputs the signal shown in FIG. 8, and when the signal first outputs H, the reset terminal R of the flip-flop circuit 54
When VCH is input, the flip-flop circuit 34 is reset, and due to the reset, the output from its output terminal Q goes from H to ! :Become.

The OR circuit 55 inputs the above output and outputs L, and inputs the output to the NOR circuit 54. However, since L is input to the NOR circuit 53, the flip-flop circuit 6
5 is the previous fall! In other words, it outputs L,
This striking output and the output from the output terminal Q of the flip-flop circuit 54 are input to the NOR circuit 61, and the NOR circuit 61 outputs H. Therefore, the AND circuit 62 receives its (1) output and the rectangular signal from the output terminal q of the 12-bit binary power counter circuit 67, and the
As described in Section 11 (II), the 12-bit binary force counter circuit 57 is repeatedly reset and released according to the output signal from the output terminal q, and the 12-bit binary force counter circuit 57 is ~Q+2 is L
It becomes a book. Therefore, when 2a8 seconds have passed since the reset of the inary counter circuit 57 for 12 pits,
The OR circuit 58 includes a flip-flop circuit 35. The batting force from the input terminal Q7 and the batting force from the output terminal Q7 of the 12-pitched inertia counter (b) path 37 are inputted to the OR circuit 58.
Outputs keL. This striking force causes the solenoid 15 to stop driving and the center gate 12 to be in the closed state. In other words? )-',' As shown in Figure 8, solenoid 1
5 is driven 18 times at intervals of 0.8 strokes, the center gate 12 is opened and closed 18 times, and the first winning probability increasing state is exercised.

While the solenoid 15 is driven at an interval of 0.8 seconds n-71, the AND circuit 70 receives the striking force from the output terminal Q of the flip-flop circuit 34 and the output terminal q of the 12-bit binary force counter circuit 67. The AND circuit 70 outputs the same output signal as the rectangular signal from the output terminal Q4. The output signal and the striking output from the flip-flop circuit 35 are input to the OR circuit 74 (the d-AND circuit 74).
A number is output to the same output signal as the output signal from 0, and the right exercise indicator lamp 52 blinks according to the H, L state of the output signal.

While the center gate 12 is repeatedly opened and closed by the driving of the solenoid 15, when 10 pachinko balls enter the prize opening 11Vc one after another, the count switch 16 is closed for each pachinko ball and the clock is set to 1, which is set to 4-bit binary. In order to output the CK ratio from the input terminal of the counter circuit 77, the output terminals Q and Q4 of the 4-bit binary counter circuit 77 output H, and both H outputs are input to the AND circuit 68. The AND circuit 68 therefore outputs H, and the H output is input to the OR circuit 67, which outputs H and inputs H to the reset terminal R of the flip-flop circuit 34. , the flip-flop circuit 54 is reset. Therefore, similarly to the above, the NOR circuit 61
outputs H, and the AND circuit 62 receives its H output and the output signal from the output terminal Q6 of the 12-bit binary force counter circuit 37; Reset/reset release is returned in response to the output signal from output terminal 1 Q6. Therefore, the output terminal Q of the 12-bit binary power counter circuit 67.

~Q1□ is in the L state and L is output from the OR circuit 58. Even if the solenoid 15 has not completed its 18th driving operation, the driving of the solenoid 15 is stopped.

When the right exercise switch 29 is closed, the AND circuit 50 outputs H as described above, but the H output is input to the reset terminal R of the flip-flop circuit 56 via the OR circuit 52, and Circuit 33 is reset.

Therefore, the output terminal Q outputs H to L, and the L output is input to the input terminal of the flip-flop circuit 640, and the flip-flop circuit 64 outputs the H output from the output terminal Q of the flip-flop circuit 63. erase the memory of. As a result, L is inputted to the AND circuit 71 from the output terminal Q of the flip-flop circuit 53, and the right reservation indicator lamp 26 is turned off.

As mentioned above, the input terminal DVc of the flip-flop circuit 34
Even if L is input, the right exercise switch 29 is closed, the AND circuit 50 outputs H, and the flip-flop circuit input terminal CVcH is input, 2a8 seconds (0,8
sec x 18 times) or the count winning switch 16 is not closed 10 times, the reset terminal R[)i of the flip-flop circuit 34 is not input, so the reset will not occur. This flip-flop circuit 34 is reset, and the output terminal Q becomes L, and L is manually input to the AND circuit 70.

When L is manually input to the AND circuit 70, the AND circuit id L is output, and the L output and the output from the flip-flop circuit 65 are input to the OR circuit 74.

Therefore, the OR circuit 74 outputs L, and the right exercise indicator lamp 32I''i stops blinking and goes out.

(Effects of the Invention) As described above, the present invention can provide a pachinko machine that is rich in game variations and stimulates the player's desire to play the H-1 game.

[Brief explanation of drawings]

FIG. 1 is a front view showing a pachinko machine according to the present invention, FIG. 2 is a schematic diagram of the front main part of the pachinko machine according to the present invention, viewed from an oblique side, and FIG. 6 is a front view showing a pachinko machine according to the present invention. Used in pachinko machines 1. FIG. 4 is a perspective view showing the connection relationship between the center gate and the solenoid; FIG. 4 is a control circuit diagram used in the present invention; FIGS.
The figures are signal waveform diagrams of the clock signals output from the 12-bit binary force counter circuit, respectively. Figure 7 is a series of signal waveform diagrams when the 1 solenoid is made to perform the second winning probability increasing state, and Figure 8 is These are a series of signal waveform diagrams when the solenoid V is caused to perform the first winning probability increasing state. 15... Solenoid 22... Prize opening 2 for securing the right
7...Kugaguchi for use by the interest bank 36...Flip-flop circuit 34...Flip-flop circuit 65...Flip-flop circuit 36...Clock oscillation circuit 57...
・12-bin input power output circuit 38... Reset circuit 39... Reset circuit 40... Reset circuit 4
2... Solenoid drive circuit patent applicant Nakajima
Ken Yoshiga 2 Figure 2 Figure 3

Claims (1)

[Claims] (1) a solenoid that increases the probability of winning; a rights securing circuit that is turned on when a pachinko ball enters the winning opening for securing rights and sets the solenoid to a first winning probability increasing state and drive preparation state; When the rights securing circuit is in an on state and a pachinko ball flies into a winning opening for rights line usage different from the winning opening for securing usage and is turned on, the solenoid is set to a first winning probability increasing state. When the right securing circuit is in the OFF state and a pachinko ball flies into the winning opening for use in the right row and turns on, the solenoid is operated 1 process higher than in the first winning probability increasing state. A pachinko machine comprising: a separation exercise circuit that drives the probability to a second winning probability increasing state.