JPS6079439A - Diagnostic control system - Google Patents

Abstract

PURPOSE:To improve the resolution of the indication of a fault unit by pointing out the fault unit on the basis of diagnostic information when a fault occurs, the output of an error display FF, and diagnostic information after the FF is initialized and then restarted. CONSTITUTION:An error display flip-flop (FF)530 is provided in one-to-one relation with fault indication units 10-50, and the FF530 connected to the register 510 of the unit 50 through a parity check circuit 511 is connected to a diagnostic controller 100 with a register 90 through a check inhibition mode FF60. The FF530 is made settable by the FF60 to make a diagnosis. For example, if a fault 120 between registers 110 and 510 is detected, the contents A of the register 90 and the output B of the FF530 at this time are stored, and the FF530 is reset after being initialized to restart the diagnosis, thereby indicating that the fault 120 is caused by the unit 10 from the current contents of the register 90 and the contents A and B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a diagnostic control method that improves the resolution of faulty unit indication among the diagnostic performance of a logic device.

[Prior art]

Conventionally, in the diagnosis method for this type of logic device, when a microdiagnosis program loaded into the control memory is started, the six registers, circuit network, random access memory, etc. that make up the logic device are checked for each microinstruction. Works with control. As a result, a plurality of check circuits arranged in the logic device operate to check the data parity on the register and the timing check of the control circuit. If there is a failure, an error indicating flip-flop provided corresponding to each of the check circuits is set, and the logic The device clock is stopped. Since these operations are executed without the knowledge of the microdiagnostic program, the diagnostic program is interrupted at any instruction step where the clock is stopped. In this case, the diagnostic results, which serve as information for pointing out a fault, are the symptom (diagnostic) information stored in a specific register of the logic device and the error display flip-flop in order to recognize the point where the diagnostic program was interrupted. Only the lit state is valid. However, since the symptom information may not always display a valid value depending on the interruption point of the diagnostic program that generates and stores the symptom information, there is a drawback that invalid symptom information is used to point out a faulty unit. Furthermore, if one error display flip-flop displays the logical sum of the check results of multiple check circuits, the diagnosis has been completed before the clock stops among the check target circuits corresponding to each of these multiple check circuits. Although it can be determined that the circuit to be checked is not affected by the failure, it is not possible to determine whether or not the circuit to be checked, which has not yet been diagnosed, is affected by the failure because the diagnostic program has been interrupted.

Therefore, when such an error display flip-flop lights up and the diagnostic program is interrupted, the faulty unit must be pointed out in a state where it is impossible to determine whether or not the fault has affected all logic circuits targeted by the check circuit.

Generally, when one error display flip-flop representatively displays the check results of multiple check circuits,
If the results of each of the plurality of checks are known, it is possible to localize the fault location very well, so the conventional fault unit pointing method has the disadvantage that resolution cannot be improved.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an entire diagnostic control system that solves the above-mentioned drawbacks and improves the resolution of faulty unit detection.

[Structure of the invention]

The method of the present invention includes a control memory for storing microinstructions, a logic circuit, a storage circuit, and a plurality of control memories for checking the normality of an output provided from at least one of the logic circuit and the storage circuit independently of the control of the microinstructions. a check circuit, a check mode prohibition flip-flop that is reset after the microdiagnosis program is stored in the control memory, and a plurality of check circuits provided in one-to-one correspondence with the plurality of check circuits when the check prohibition mode flip-flop is reset. a logic device having a plurality of error display flip-flops to which check results are set; and a logic device having a memory lJ' for resetting the check inhibit mode flip-flop in response to occurrence of a failure in the logic device and performing the microdiagnosis. The program is started, and the diagnostic information stored in a specific register in the logic device as a diagnosis result is stored in the memory together with the output of the error display flip-flop as first diagnostic information, and then the logic device is initialized and set. Then, the check prohibition mode flip-flop is set, the micro-diagnostic program is restarted, and the diagnostic information stored in the specific register as the diagnostic result is stored in the memory as second diagnostic information, and then the diagnostic information is stored in the memory. and a diagnostic control device that controls a diagnostic operation for pointing out a faulty unit of the logic device based on the first diagnostic information, the output of the error display flip-flop, and the second diagnostic information. Features.

[Embodiments of the invention]

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, the logic circuits to be diagnosed in the logic device to which the diagnosis method of the present invention is applied are the units 10, 20, 30, 40, . and 50. It consists of a check prohibition mode flip 70 (hereinafter referred to as F/F) 60 and an OR gate 70. (Union to disaster)
10, 20.30° 40 and 50 are each register 11
0,210°310.410. and 510, and has registers 110.210, 310 . and 410 are connected via a selector 520 to a register 510 that can be read by a microinstruction. The register 510 includes a parity check circuit 511 and an error display flip 70 (hereinafter referred to as F/F) 5 that displays the parity check result.
30 are connected. A signal is given to the error display F/F 530 from the check prohibition mode F/F 60 through the OR gate 54 (l) in order to set the error display F/F, and in response to this signal, a logic signal is sent through the OR gate 70. A clock stop signal 710 is output to a clock control section (not shown) of the device. The clock stop signal 710 is applied to the OR gate 540 in addition to the output of the check prohibition mode F/F 60. The check prohibition mode F/F 60 is connected to the diagnostic control device 100 via a signal line 61, and its set conditions are controlled from the diagnostic control device 100.

Register 90 in FIG. 1 is a microinstruction writable register whose output can be read by diagnostic control device 100. Register 90 in FIG. □Register 90 is used by a microdiagnosis program to be described later to store symptom information in order to identify the current test content. The symptom information stored in the register 90 in the micro-diagnosis program shown in one embodiment of the present invention is divided into two parts: the first half is a test unit number for identifying a plurality of test units constituting the diagnostic program, and the second half is a test unit number for identifying a plurality of test units making up the diagnostic program. It is assumed that test results (hereinafter referred to as error vectors) for each of a plurality of checkpoints existing in each test unit are stored.

Before explaining all embodiments of the microdiagnosis control system of the present invention, the flow of a microdiagnosis program for diagnosing the logic circuit shown in FIG. 1 will be explained with reference to FIG.

Note that FIG. 2 only shows the part for diagnosing the circuit shown in FIG. 1, and omits the flow of the microdiagnosis program regarding other logic circuits existing in the logic device to be diagnosed.

First, in step 8o, a test unit number that uniquely identifies the inter-register transfer test is stored in the first half of the wampton information storage register 90 in FIG. Next step 81
, 82, 83, 84. and register 110 by 85
and 510, 210 and 510, 310, 510, 410 and 510 are performed. First, among the bits of the error vector assigned to the symptom information in step 81, a bit value "1#" is set at a position appropriate for the specific register-to-register transfer test that is currently being focused on, and then the test is performed in step 82. Next, the register 510 and the correct value are compared in step 83, and if they match, the bit value ''' is stored in the corresponding bit position of the error vector set in step 81 in steps 84 and 85.
θ'' is set, and if the result of the comparison does not match, step 85 is skipped.The above operation is repeatedly executed for each unique register transfer test in step 86, and in step 87, all unique registers are The error vector which is the test result of the inter-transfer test is referred to, and if a failure is detected in at least one test, step 89 is executed without starting a new test 88t, and the diagnostic program is stopped.

Now, the present invention's my/') argument control method is shown in FIG. 1 again.
The explanation will be given with reference to FIG. 2 and also FIG. 3 showing a flowchart of the diagnostic control program in the diagnostic control device 100.

Referring to FIG. 3, first, in operation step 91, the second
A diagnostic program that operates as shown in the figure is loaded into the control memory and is activated in operation step 93. Prior to this operation, operation step 92
The check prohibition mode F/F 60 shown in the figure is reset. Referring to FIG. 1, this state indicates that a logic 0 is applied to the hold terminal H of the error display F/F 530 through the gate 540t.
The output signal from the parity check circuit 511 can be set to the error display F/F 530. Now, in the circuit shown in FIG.
Failure 1 on the data path between unit 10 and unit 10
Assuming that 20 exists, this fault is detected and pointed out in the following procedure.

In step 82 of the diagnostic program shown in FIG. 2, an inter-register transfer test between the registers 110 and 510 is executed, but the parity check circuit 511 detects a failure 120 and the corresponding error display F/F 530 is set. be done. Error display F/F530 output is OR gate 70t
- The clock of the logic device to be diagnosed is stopped because it is output as a clock stop signal 710. For this reason, the diagnostic program performs step 82 of the diagnostic program in FIG.
Interrupt in the middle. At this time, clock stop signal 7 in Figure 1
10 is OR gate 540f: error display F/F via
By supplying a logic 1 to the hold terminal of the error display F/F 530, the error display F/F 530 can maintain its logic state until the clock stops. Furthermore, the clock stop signal 710 is the current error display F/F 530
Since the logic 1t is simultaneously supplied to the hold terminals H of all other error display F/Fs 530' to 53σ, the other error display F/Fs 530' to 53σ have the logic state at the time when the failure 120 is detected. It can be held until the clock is stopped. This causes error display F/F
The effects of fault 120 are prevented from propagating into the logic device from the time 530 lights up until the clock of the logic device stops. Clock stop signal 7 shown in FIG.
With further reference to No. 10, the signal is the aforementioned error indication F.
/F530 Any other error display F/F530
It is also valid when '~530' is set, but this means that a failure detected by any other error check circuit other than the error check circuit 511 corresponding to the error display F/F 530 causes the error display F/F to This is to prevent the information from being transmitted to 530.

Now, according to the conventional diagnostic control method connected by the broken line in FIG. 3, the diagnostic operation ends with the above operation, and the contents of the register 90 at this time are displayed by the diagnostic control device 100 as symptom information 1 on the error display F/F. Together with 530, a faulty unit is identified in the operating step 94 shown in FIG. 3 and in the subsequent operating step 99.

However, as shown in the flowchart of the diagnostic program in Figure 2, register 2 is the error vector that reflects all the results of the transfer test between each unique register assigned in the symptom information.
10 and 510, 310 and 510° and 410 and 51
Information between 0 and 0 is undefined because the test has not been performed.

Therefore, such an error vector cannot be used as input information to indicate a faulty unit, but only from the number of the register-to-register transfer test unit in the symptom information and the information that the error display F/F 530 is lit. Then, as a failed unit, 10, 20, 30°40
, and 50'i must be pointed out at the same time.

Furthermore, even if the diagnostic program is modified to assign a unique test unit number to each unique register-to-register transfer test, the transfer test unit number between registers 110 and 510 and the error display F/F 530 light up. Based on this information alone, it is necessary to simultaneously identify unit 10 and unit 50 as faulty units.

However, according to the diagnostic method of the present invention, the faulty units 10 and 5
0 can be separated as follows, and the resolution of faulty unit indication can be improved. Referring again to FIG. 3, the above-mentioned logical device to be diagnosed has an error display F/F.
Even if the cycle clock is stopped due to the lighting of 530, the microdiagnosis program that performs the nine operations shown in FIG. 2 is started again in operation step 96. This operating step 96 requires preparation before operating step 95. That is, in operation step 95, the various registers, circuit networks, and error display F/F't in the logic device to be diagnosed are initialized to the same state as when the first microdiagnosis program was started, and then checked. Prohibited mode F/F60
is set. This condition is an error display F/F 530
By supplying logic 1t- to the hold terminal H of
Even if the integrity check circuit 511 detects a failure, it operates so as not to set the error display F/F 530e. Therefore, when the microdiagnosis program is restarted in step 96, the error message F/
Since the F 530 does not light up, the diagnostic program is not interrupted and all specific register-to-register transfer tests can be completed.

Referring to FIG. 2, due to the currently assumed fault 120, the error vector in the symptom information is such that the corresponding bit of the test result between registers 110 and 510 is @1'' (fault detection), and other residual combinations The test result corresponding bit is ′θ″
(fault not detected), step 8 of the diagnostic program
7. and 89, the microdiagnosis program is automatically stopped.

After this, in operation step 97 of FIG. 3, the symptom information is collected as symptom information 2 in register 90, and in the subsequent operation step 98, the faulty unit is pointed out. Since the above-mentioned symptom information 1 and the current symptom information 2 have the same test unit number for the register-to-register transfer trial, the error vector information in the symptom information 2 is determined to be valid, and therefore, the failure is caused by the register. 11
Because of the phenomenon that it affects only the transfer test between 0 and 510 and does not affect the transfer test between other registers, it becomes possible to exclude 50 as the pointing unit and point out only 10.

Next, if the test unit numbers in symptom information 1 and symptom information 2 do not match, when pointing out a failure, sacrifice resolution only from the test unit number in symptom information 1 and the lighting error display F/F. This shows that it is possible to point out a faulty unit without any problems.

First, an environment in which a phenomenon occurs in which the test unit numbers in symptom information 1 and symptom information 2 do not match will be described.

Referring to FIG. 4, in a second embodiment of the present invention, registers 110.210.310.410° and 51
02 selector 520. The parity check circuit 5111 and error display F/F 530 are all the same as shown in FIG. 1, but the point shown in FIG. This is different from the first embodiment. In Fig. 4, error display F/F53 (l
Controlling game) 540. Check prohibition mode F/F
60 and a clock stop signal 710 to a clock controller (not shown), the functions are the same as the like numbered components of FIG. Now, suppose that there is a fault 120f on the data path between register 110 and register 510 in the circuit shown in FIG. Time parity check circuit 5
11 and the result is an error display 1i'/l;"
530.

Satoru 11 Shiban Moya Shinto L If point - I I to 1 C.) Error display F/F when running the Darkness 7th Second Experience unit
It is not possible to point out the faulty unit 1 from the information that 530 is lit.In this situation, the faulty unit 120 is connected to the
0, between registers 310 and 510, and between registers 410 and 510, there will be no change at all. Therefore, we show that by creating an error vector that reflects the test results of the transfer test for each combination of registers in a microdiagnostic program, it is possible to uniquely point out the faulty unit 1 without being aware of the combination of registers in which the fault was detected. There is.

As in this example, even if the test results of multiple checkpoints that make up a test unit are unknown, the faulty unit is uniquely 0.
If 1 can be pointed out, the step of creating an error vector is deleted in the diagnostic program. Furthermore, in a test unit that does not create an error vector, there are only microinstructions that operate the circuit under test, and there is no step to judge the test results, so the microl diagnosis program automatically runs as shown in the flowchart shown in Figure 2. There is no function to stop it. Therefore, when the diagnostic control method of the present invention is applied to the circuit shown in FIG. The unit number and the lighting information of the error display F/F 530 are collected. Next check prohibition mode F/F 60
When re-executing the diagnosis in a state where is set, as described above, there is no step in the register-to-register transfer test unit of the diagnostic program to detect a failure and automatically stop the program, so the process proceeds to the next test unit. Therefore, a phenomenon occurs in which the test unit number in the symptom information 2 is always stored with a different value from that in the symptom information 1.

As can be seen from this example, if the unit numbers in the two symptom information are different, the faulty unit can be pointed out from the unit number in the first symptom information 1 and the illuminated error display F/F without sacrificing resolution. .

In other words, symptom information 2 may be ignored.

〔Effect of the invention〕

The diagnostic method of the present invention includes symptom information 1 when the diagnosis is executed using the conventional diagnostic method, an error display flip-flop, and a symptom information when the diagnosis is re-executed with the error display flip-flop's Seratra disabled. By inputting the information 2 and pointing out a faulty unit, there is an effect that the pointing resolution can be improved.

[Brief explanation of drawings]

1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the flow of a diagnostic program to explain the operation of FIG. 1, and FIG. A diagram showing the flow of control and FIG. 4 are diagrams showing a second embodiment of the present invention. In the figure, 10, 20, 30, 40, 50 degrees 1...
...Faulty unit, 110, 210, 310° 410
．． 510.90...Register, 511...
...Parity check circuit, 60...Check prohibition mode F/F, 53G...Error display F/
F180~89...Diagnosis program step,
91-99...Diagnostic operation step, 100...
...Diagnostic control device. To~＼ Figure I Figure 2

Claims (1)

[Claims] A control memory for storing micro-instructions, a logic circuit, a storage circuit, a plurality of check circuits for checking the normality of an output provided from at least one of the logic circuit and the storage circuit, independently of control of the micro-instructions, and the control. A check mode prohibition flip-flop that is reset after the microdiagnosis program is stored in the memory is provided in one-to-one correspondence with the plurality of check circuits, and the check results of the plurality of check circuits are set when the check prohibition mode flip-flop is reset. a logic device having a plurality of error indicating flip-flops, and a memory IJ? In response to the occurrence of a failure in the logic device, the check inhibit mode flip-flop is reset, the micro-diagnosis program is started, and the diagnosis information stored in a specific register in the logic device is used as a diagnosis result for a first diagnosis. The information is stored in the memory along with the output of the error display flip-flop, and then, after initializing the logic device, the check prohibition mode flip-flop is set and the micro-diagnosis program is restarted, and the diagnosis result is stored in the specific register. The stored diagnostic information is stored in the memory as second diagnostic information, and the second diagnostic information is then based on the first diagnostic information stored in the memory, the output of the error display flip-flop, and the second diagnostic information. A diagnostic control system comprising: a diagnostic control device that controls a diagnostic operation that indicates a failure unit of the logical device.