JPS6080310A - Alc circuit - Google Patents

Abstract

PURPOSE:To generate a proper ALC voltage in response to the type of a radio wave by controlling a switching circuit with an output signal frequency-divided by a programmable counter so as to switch a charge/discharge circuit in a time constant circuit. CONSTITUTION:A programmable counter 18 frequency-divides a signal from a pulse generator 20 by programming a frequency dividing ratio in response to the selective operation by a digital mode selecting means 11 so as to control a switching means Q1 of the charge/discharge circuit 21 so as to make the time constant proportional to the sum of pulse widths per unit time. The ALC voltage transmitted from an ALC voltage generating circuit 9 to a base of a transistor Q2 for amplification controls an ALC line connected to a variable gain amplifier 5 according to the time constant of a terminal 21b for time constant.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ALC circuit.
The present invention relates to an ALC circuit that can change the holding time of an LC voltage.

Usually 1. The ALC circuit is provided in a transmitting circuit such as a wireless communication device for protecting the transmitting final stage section 6 shown in FIG. The transmitting circuit includes a transmitting device 1, a pre-stage transmitting circuit 4, and a variable gain amplifier 5.
, a transmission final stage section 6, and an antenna 7. Telephone key 2 of transmitter 1 (including automatic transmitter), microphone 3
The transmission signal generated by the above is output to the preceding stage transmission circuit 4. On the other hand, operation A? Mode selection button 1 provided on panel 11
Positive or negative pulse generated by operations 3 and 14 1.1 -? −? The signal output is sent as mode data to the preceding stage transmitting circuit 4 via the data bus. The front-stage transmission circuit 4 outputs the input transmission signal to the transmission final stage section 6 via the rear-stage variable gain amplifier 5 without performing waveform processing such as modulation, amplification, and mixing according to the mode data. The transmission final stage unit 6 generates high frequency transmission power from the input transmission signal and radiates it into the air as a radio wave from the antenna 7. This radio wave type includes modulation type (amplitude two-phase, base pulse, etc.) and transmission type (telegraph, etc.).

For amateur radio, there are attributes related to AM, FM, SSB upper sideband,
SSB lower sideband, CW, FSK (Frequency shift keying using SSB, AM, i.e. audio FSK
...including AFSK gold). The high-frequency transmission power may be one that does not involve a carrier wave, such as SSB, or one that is binary or two-frequency, such as code communication, and each has its own unique ALC voltage fluctuation. For this reason, AL
A circuit has been proposed in which the ALC voltage generated from the ALC voltage generation circuit 9 is controlled by the output of the pulse integration counter 16 so that the C voltage can be generated in accordance with the above modes, but the output of the pulse integration counter 16 is in digital form. Therefore, it has the disadvantage that it cannot control the ALC circuit 8 equipped with analog control.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide an ALC circuit that generates an appropriate ALC voltage depending on the type of radio wave.

Φ The present invention is provided with a programmable counter whose frequency division ratio is programmed in response to the selection operation by the digital mode selection means. The switching circuit is controlled by the output signal frequency-divided by the programmer sol counter, and the charging/discharging circuit of the time constant circuit is switched.

An embodiment of the ALC circuit according to the present invention will be described below with reference to FIG.

In FIG. 2, reference numeral 16 indicates a pulse integration counter. An addition pulse or a subtraction pulse is input to the pulse integration counter 16, and mode data corresponding to the integrated value is generated. The mode data is sent to the preceding stage transmitting circuit 4 and the decoder/17 via data buses 16a and 16b.

The programmable counter 18 is programmed according to the divided data input in parallel from the decoder 17 via the data bus 17m.The pulse input from the Q pulse generator 20 to the t4 pulse terminal of the programmer counter 18 is The frequency is divided by 18 and the inverter 1
9 to the terminal 21a of the variable time constant circuit 21 as a frequency divided signal.

The variable time constant circuit 21 has terminals 21m and 21b, where the terminal 21m is a frequency-divided pulse input terminal and the terminal 21b is a time constant terminal. One end of the time constant capacitor C1 is connected to the reference potential point, and the other end is connected to the terminal 21b together with one end of the resistor R1.◎Q! The other end of the resistor R1 is connected to the collector of the switching transistor ←, and the emitter is connected to a bias circuit consisting of resistors R3+R4. Therefore, the emitter is at the level of bias voltage VB0 Transistor Q1
The base of is connected to the terminal 21a. Note that the resistor R2 provided between the emitter of the transistor Ql and the terminal 21b has a much larger resistance value than the resistor R1.

The ALC voltage sent from the ALC voltage generation circuit 9 to the pace of the amplification transistor Q2 is applied to the variable gain amplifier 5 according to the time constant of the time constant terminal 21b connected to the collector.
Controls the ALC line connected to etc. In the figure, reference numeral 12 is a drive control button, and 15 is a pulse integration counter.

Here, if the level of the transmission signal from the variable gain amplifier 5 to the transmission final stage section 6 is normal, the ALC voltage generation circuit 9
Does not generate C voltage. Therefore, the transistor Q2 is turned off, and the pALC line terminal 21b is maintained at the level of the bias voltage VB with the capacitor C1 being charged. In this case, the charge in the capacitor C1 is not affected by the switching operation of the switching transistor Q1.◎When the level of the transmission signal to the transmission final stage 6 rises and becomes higher than the comparison voltage of the ALC voltage generation circuit 9, the ALC
The voltage conversion circuit 9 generates ALC@ pressure. This ALC
Transistor Q2 becomes active due to voltage (jl) ALC
The line becomes a reference potential point. Capacitor C1 transitions from a charging state to a discharging state. When the overlevel of the transmission final stage section 6 is eliminated and the normal state is restored, the transistor Q2 becomes inactive and the reference potential point connected to the JALC line is cut off. Therefore, the charge in the capacitor C1 increases in proportion to the time that the resistor R and the transistor Q1 are on, and when charging is completed, the ALC line reaches the level of the bias voltage VB.

In the above embodiment, the frequency of the divided pulse input to the pace of the transistor Q1 is changed, but the pulse width may also be changed at the same time based on the divided frequency data.

The ALC circuit according to the present invention switches a programmable counter whose division ratio is programmed in response to a selection operation by a digital mode selection means, a switching means controlled by an output signal frequency-divided by the programmable counter, and a charging/discharging circuit. Since the structure is equipped with a time constant circuit that is switched by means, the time constant is A? It has a feature that is proportional to the statistics of the loop width.

Therefore, the time constant can be changed over a wider range than in the past, and an ALC voltage suitable for the mode can be generated. In addition, effects such as ease of incorporation into digitized radio communication devices of CombitaAID can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional ALC circuit, and FIG. 2 is a block diagram including a partial circuit diagram showing an embodiment of the ALC circuit according to the present invention. In the figure, 1 is a transmitting device, 2 is a telephone key, 3 is a microphone, 4 is a pre-stage transmitting circuit, 5 is a variable gain amplifier, 6 is a transmitting final stage, 8 is an ALC circuit, and 9 is an ALC
Voltage generation circuit, 1o is a time constant circuit, 11 is an operation panel,
12 is a drive control button, 15 and 16 are nozzle integration counters, 17 is a decoder, 18 is a programmable counter, 19 is an inverter, 2o is a nof pulse generator,
21 is a time constant circuit, cl is a capacitor, R1-R4 are resistors, and Q11Q2 are transistors. Patent applicant: Yaeshu Musen Co., Ltd. Figure 1 Figure 2

Claims (1)

[Claims] 1. variable gain amplification means; ALC voltage generation means for outputting an ALC voltage that controls the gain of the variable gain amplification means;
It is equipped with a time constant circuit that holds the ALC voltage, and a digital mode selection means that selects the radio wave type of the high frequency transmission power output from the transmission final stage, and according to the ALC voltage via the time constant circuit. In an ALC circuit related to a transmission circuit configured to control the gain of the variable gain amplification means and protect the transmission final stage, a frequency division ratio is programmed in response to a selection operation by the digital mode selection means. a grammatical counter; a switching means controlled by an output signal frequency-divided by the grammatical counter; and a time constant circuit whose charge/discharge circuit is switched by the switching means; An ALC circuit characterized in that it is configured to change a time constant of an ALC voltage depending on a mode.