JPS6080814A - Automatic offset correcting circuit for camera - Google Patents

Abstract

PURPOSE:To enable automatic correction of an offset voltage and compensation of a temp. drift by correcting the value of an offset register by a central processing unit using the offset voltage outputted by a sample holding circuit. CONSTITUTION:The output from a CCD sensor 1 is fed to a sample holding circuit 2 and the samples are held for each of a video component and a dark component, the difference between both is calculated. An offset correcting circuit 3 corrects the offset error outputted by the circuit 2. One among the respective output signals of a Bv circuit 4, an Av circuit 5, an Sv circuit 6 and an offset correcting circuit 3 is selected and outputted by a multiplexer 7. The output of the multiplexer 7 is converted to a digital signal by an A/D converting circuit 8 and a prescribed calculation is performed with a central processing unit 9, by which the offset voltage is corrected. The automatic correction of the offset voltage is thus made possible and the temp. drift is made compensatable.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides: - an automatic focusing device for an eye reflex camera that automatically corrects offset voltage that occurs when processing a digital signal obtained by A/D converting the output of the automatic focusing sensor; related to circuits.

The following types of conventional single-lens reflex cameras are known. In other words, part of the light that has passed through the lens is guided to the bottom of the mirror box, an autofocus sensor is installed at the bottom of the mirror box, and the photoelectric output from the autofocus sensor is calculated by an electronic circuit to calculate the contrast or phase difference. By detecting this, the current focus position is displayed in the finder or an automatic focusing lens is operated.

On the other hand, in recent electronic circuits, the number of digital ICs that process digital signals is increasing because of their resistance to noise, high precision, and ease of handling. In fact, single-lens reflex cameras with built-in microcomputers have also been commercialized. and,
The digital circuits are becoming increasingly complex because they also perform other processing such as exposure calculations.

Furthermore, since the autofocus sensor has a large number of photoelectric elements, the output time from each sensor is short, and A/D conversion takes a relatively long time. /D conversion and converts it into a digital signal.

By the way, an operational amplifier and other circuits are used to sample and hold the output of the autofocus sensor mentioned above.
The offset error varies greatly depending on the operational amplifier and circuit configuration. If the video signal is A/D converted without performing the offset adjustment, the video signal value on which the offset voltage is superimposed will be A/D converted, which is not preferable.

To this end, conventionally, a device using a so-called trimming resistor has been adopted in which the resistance value is adjusted each time by offset of an operational amplifier.

However, although this device can correct operational amplifiers with different offset voltages, there is a problem in that adjustment is required, and there is also a problem in that temperature drift cannot be corrected.

The present invention has been made in view of the above conventional problems, and provides an automatic camera offset correction circuit that can automatically correct offset voltage and compensate for temperature drift. be.

In order to achieve this object, the present invention connects an offset register to the output terminal of a sample-and-hold circuit, A/D converts the offset voltage outputted by the sample-and-hold circuit, and uses this output value to control the offset register. The value is changed by the central processing unit to correct the offset voltage, and the offset voltage is controlled to a predetermined value.

Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. This figure is a block diagram showing part of the electronic circuit of a single-lens reflex camera including an automatic focusing circuit. The CCD sensor 1 is provided at the bottom of the mirror box and receives light from a subject. The output of this CCD sensor 1 is
The signal is sent to the sample and hold circuit 2, where the video component and dark component are sampled and held separately, and the difference between the two is calculated. That is, the difference is output as a video signal.

The offset correction circuit 3 corrects the offset error output from the sample hold circuit 2. Multiplexer 7 has 8■circuit 4%, AVOO path 5, Sv circuit 6
, the offset correction circuit 3, and selects and outputs one of them. It converts the output of the A/D conversion circuit 8 multiplexer 7 into a digital signal, and this converted signal is sent to the central processing unit! !
9, and predetermined calculations are performed. Note that this central processing unit 9 includes a CCD sensor 1, a sample hold circuit 2, an offset correction circuit 3, a multiplexer 7, an A/
D-transformation circuit 8 is controlled.

FIG. 2 is a circuit diagram in which the multiplexer 7 in FIG. 1 is omitted and specifically shows the flow of the CCD sensor. A constant current source 13 is connected to the output terminal of the CCD sensor 1. The analog switch 11 is provided between the CCD sensor 1 and the non-inverting input terminal of the operational amplifier 16, and its control terminal is connected to the central processing unit @9. Further, the analog switch 12 is provided between the CCD sensor 1 and the non-inverting input terminal of the operational amplifier 17, and its control terminal is connected to the central processing unit 9. Capacitors CI and C2 are connected to non-inverting input terminals of the operational amplifiers 16 and 17, respectively.

Further, the analog switch 14 is provided between the reference voltage source 40 and the non-inverting input terminal of the operational amplifier 16, and its control terminal is connected to the central processing unit 9. Further, the analog switch 15 connects the reference voltage source 40 and the operational amplifier 1.
7, and its control terminal is connected to the control terminal of the analog switch 14.

The sample and hold circuit 18 includes the analog switch 11.
14, a capacitor C1, and an operational amplifier 16. Further, the sample hold circuit 19 includes an analog switch 12.15, a capacitor C2, and an operational amplifier 17. These sample and hold circuits 18 and 19 correspond to the sample and hold circuit 2 in FIG. A series resistor of resistors R1, R3, and R2 is connected between the output terminals of the operational amplifiers 16 and 17, a connection point between the resistors R1 and R3 and an inverting terminal of the operational amplifier 16 is connected, and a connection point between the resistors R2 and R3 is connected. and the connection point of
It is connected to the inverting terminal of the operational amplifier 17.

Further, a resistor R4 is connected between the output terminal of the operational amplifier 16 and the non-inverting input terminal of the operational amplifier 20, and a resistor R5 is connected between the output terminal of the operational amplifier 17 and the inverting input terminal of the operational amplifier 20. A resistor R6 is connected between the inverting input terminal and the output terminal of the operational amplifier 20, and a resistor R7 is connected between the non-inverting input terminal and the reference voltage source 40. A resistor R8 is connected between the output terminal of the operational amplifier 20 and the inverting input terminal P of the comparator 26, and a constant current source 21 is provided between the power supply terminal Vcc and the inverting input terminal of the comparator 26. And constant current source 2
2 and analog switch 27, constant current source 23
A series circuit of the constant current source 24 and the analog switch 29 , a series circuit of the constant current source 25 and the analog switch 30 , a series circuit of the constant current source 24 and the analog switch 30 ,
connected between the inverting input terminal and ground.

For example, if the current value of the constant current '1fA25 is I/8, then the current values of the constant current sources 24, 23, and 22 are respectively I/4.1/2.1, and so on. 2
5.24.23.22 have a relationship in which the current values are integral multiples.

The offset register 31 is controlled by the central processing unit 9 via a 4-bit bus, and controls analog switches 27, 28, 29, and 30 via each control terminal. These constant voltages 11f121, 22°23.24.2
5, the analog switches 27, 28, 29, and 30, the resistor R8, and the offset register 31 constitute the offset correction circuit 3 shown in FIG.

The output terminal of the comparator 26 is connected to a successive approximation register 32, and the output signal of this successive approximation register 32 is D
The signal is sent to the non-inverting input terminal of the comparator 26 via the /A converter 34, and is also sent to the central processing unit @9.

The D/A converter 34 receives a reference voltage Vr from a reference voltage source 40.
ef is supplied. Successive approximation register 32 is driven by a clock signal from clock generator 33.

Comparator 26, successive approximation register 32, and D/A
converter 34, clock generator 33, and reference voltage source 40
The A/D conversion circuit 8 shown in FIG. 1 is configured by these. This A/D conversion circuit 8 is of a successive approximation type.

First, since the output format of the CCD sensor 1 is an open drain format, the output voltage of the CCD sensor 1 is extracted by connecting the constant current source 13 to the train. The output signal of the CCD sensor 1 consists of a dark signal and a video signal component superimposed on this dark signal. For this reason, the dark signal and the video signal are once separated and extracted, and then the difference between them is calculated and used as the video signal. The output signal of the CCD sensor 1 is converted into a dark signal and a video (
It is divided into it numbers and each is sampled. Then, the dark signal Vd and the video signal VV are held in the capacitors C1 and C2, respectively.

Next, resistors R4, R5, R6, R7 and operational amplifier 2
The difference between the dark signal Vd and the video signal Vv is outputted by the differential amplifier circuit configured as 0. Here, one end of the resistor R7 is connected to the reference voltage V r
It becomes ef.

Here, the value of the resistor R4 and the value of the resistor R5 are set to be the same, and the resistor R
6 and R7 are the same, and the operational amplifiers 16 and 17
．． 20 input offset voltages, VO31 and V
O32 and VQS3, the final output voltage Vout of the operational amplifier 20 is Vout = (R6/R4) (
1+(R1+R2)/R3) (Vv-Vd+Vos2
-Vosl )+ (1+ (R6/R4) ) ・V
os3 +Vref −−−−−−−−■.

Next, make the value of resistor R1 and R2 the same, and resistor R4
When the value of and the value of R6 are made the same, the control signal φO8 is set to Hl, and the input voltage of the sample and hold circuits 18 and 19 is set to the reference voltage source 40 and the reference voltage ref, V V = V d = Since V ref,
Its output voltage vout is Vout = (1+2・R
1/R3) ・(Vos2−VO8+)+2・V 03
3 + V ref・・・・・・・・・・・・・・・・
... becomes ■. Therefore, the offset voltage V off
set is Vorfset −(1+2 ・R1/R3
) ・(Vos2-VO81)+2 ・Vos3 ・・
・・・・・・・・・・・・・・・・・・・・・・・・
■It becomes.

Here, if the input configuration of the operational amplifier 16.17 is FET input, the offset voltage of the operational amplifier 16.17 alone will be approximately ±30 mV. Also, ignoring the offset voltage of the operational amplifier 20, (1+2・R1/
When R3) is set to 1, the offset voltage of the entire offset correction circuit 3 becomes ±60111v at maximum.

Next, the current value of the constant current +1!21.22 is set to 1, and the current value of the constant current sources 23, 24, and 25 is set to 1/2. [
/4. Let it be I/8. Also, constant current source 22.23.24
．． 25 are all off, the current ■ of the constant current source 21 flows through the resistor R8 to the operational amplifier 20, and the potential at point P becomes Vout + l-R8, l-R
The potential at 8 minutes increases. Further, for example, when the constant current sources 22 and 23 are on, a current of 1/2, which is the difference from the current flowing through the constant current source 21, flows from the operational amplifier 20 to the constant current source via the resistor R8, and the current flows from the operational amplifier 20 to the constant current source through the resistor R8. The potential is Vo
It becomes ut -1・(,R,8)/2. Therefore, when the inputs of the sample and hold circuits 18 and 19 are set to the same potential, the potential vP at point P is VP=(1+2・
R1/R3) (Vos2-Vosl) +2-Vos
3 +Vref + (1-al-1-R2-1/2-
R3-I/4-R4-1/8) R-■. However, al, R2, R3, and R4 take a value of 0 or 1 depending on the state.

Therefore, by appropriately determining al, R2, R3, and R4, the voltage can be changed from +IR to -(7/8)IR, and the offset value of the first and second terms of the equation It is possible to correct the

Note that the resolution of this D/A conversion part is (1/8)·R, and by increasing the number of registers, switches, and constant current sources in the offset correction circuit 3, the resolution can be increased and the offset adjustment The range can be expanded.

In this way, by superimposing a predetermined D/A converted voltage on the sampled and held video signal@value,
The offset voltage can be corrected.

Then, the output from which the offset has been removed is sent to the A/D conversion circuit 8.
send to The central processing unit 9 controls the CCD sensor 1, the analog switches 11, 12.13° 14, and the offset register 31 in the offlet correction circuit 3, and controls the A/D
A signal from the conversion circuit 8 is received and subjected to screening processing.

FIG. 3 is a time chart of the above embodiment, and FIG. 4 is a flow chart of the above embodiment.

The manner in which offset correction is executed in response to a command from the central processing unit 9 will be described with reference to FIG. 3.4.

Note that the resolution of the A/D conversion circuit 8 and the central processing unit 9 is a general 8-bit configuration. First, before sampling and holding the value of the CCD sensor 1, offset correction is performed immediately before the start of integration in order to complete the offset correction. Of course, the signal φds and the signal φ sent from the central processing unit 9 to the analog switches 11 and 12, respectively.
By setting VS to LO, signals from the CCD sensor 1 side to the sample and hold circuits 18 and 19 are cut off.

The signal φ is then sent to the analog switch 14.15.
By setting O8 to Hl, the input of the sample and hold circuit 18.19 is set to the reference voltage V ref. In this case, the output of the operational amplifier 20 is you shown in equation (■).
It becomes t.

Here, the contents of the offset register 31 are initialized to oooo by a command from the central processing unit 9. In this case, the constant current sources 22, 23, 24, 25 are all turned off, and the current I of constant current #+21 flows to the operational amplifier 20 via the resistor R8. In other words, in formula 0, ai=82
=83=84=o, and the potential at point P is VP=V
It becomes out + I - R8. This value is converted into a digital value by the A/D conversion circuit 8 and input to the central processing unit 9. On the other hand, the reference voltage V ref corresponds to an A/D converted value. oooooooo is stored in advance in the central processing unit, and these two values are compared.

Here, if the A/D converted output value is higher than v rat, an overflow occurs and the output becomes 00, so the contents of the register are incremented by 1 and the same operation is repeated. If the A/D conversion value is a value other than 00H,
At that time, since yrer has not been reached, the value of the offset register is in the state of oooo, and the offlet correction has been completed.

Next, the contents of the register are increased by 1 several times and A/D conversion is repeated, and if the value changes from 00H to any other value, then the output value changes from a value greater than vrer to a value greater than that Vref. has also become a small value, and the central processing unit 9 stores the value of the offset register 31 at that time, thereby completing the offset correction. Even if the contents of the register reach 1111, the A/D conversion value will be 0.
If it does not change from 0H, offset register 1
The correction operation is completed by considering the contents of No. 11 as the best value.

In the above explanation, the A/D conversion circuit 8 is used to correct the offset error of the sample and hold circuits 18 and 19. Comparator 2 provided in the converting circuit 8
6 and the reference voltage source 40 may be used. That is, when correcting the offset of the sample and hold circuits 18 and 19, the comparator 26 is separated from the successive approximation register 32, and the output signal of the comparator 26 is applied directly to the central processing unit 9. The non-inverting input terminal of the comparator 26 is also disconnected from the D/A converter 34, and the non-inverting input terminal is connected to the output of the reference voltage source 40.

The operation in this case is also similar to the flowchart shown in FIG. Further, the reference voltage V
ref and the voltage at point P will be compared. The contents of the offset register 31 are o.

The output of the comparator 26 gradually changes from 00 to LO.
Offset register 3 when changing from to Hl
By storing a value of 1, the offset correction operation ends. Since this embodiment has a faster response time than the embodiment shown in FIG. 2, it has the advantage that the burden on the central processing unit 9 when performing other calculations is reduced.

Further, the timing for performing the offset correction may be set when the power is turned on, or may be set at regular intervals in accordance with the output timing of the CCD sensor 1. Furthermore, it is not affected by temperature drift even when the temperature changes. In addition, A/D conversion by the A/D conversion circuit is performed in the case of offset correction or c CD
The process is performed not only for the sensor 1 but also for the 3v circuit 4, Sv circuit 5, and AV circuit 6, so it is very efficient.

Offset correction is performed when there is no output from sensor 1. At that time, the control signal φO8 is set to l(i, the input of the operational amplifier 16.17 is set to V ref,
Correct the offset value included in the output value according to the formula. Therefore, if there is no offset, v out
- Become a rer.

Note that the offset voltages of the sample and hold circuits 18 and 19 and the differential amplifier circuit are A/D converted in the A/D conversion circuit 8, and this converted value and the A/D converted value 00H of the reference voltage Vref are sent to the central processing unit. 9 to be compared. Then, a command is sent from the central processing unit 9 to the offset register to change the value of the register. The value of Vp at this time is A/D converted again and compared. Repeat these operations. Further, depending on the case, it is also possible to start the value of the offset register from 1111 and lower Vp below the reference voltage V ref to set the reference voltage V ref from a low value.

At this time, with only one A/D conversion, the reference voltage V
It is also possible to know how far in advance of ref it is, and through the processing of the central processing unit 9, change the value of the offset register to complete the correction.

As described above, the present invention can automatically correct offset errors in the sample and hold circuit, and when the resolution is insufficient, the resolution can be improved by increasing the number of bits in the D/A conversion means. It has the effect of being easily improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, and is a diagram showing the electronic circuit of a single-lens reflex camera, and Fig. 2 is a concrete example focusing on the flow of the COD line sensor that performs offset correction in Fig. 1. FIG. 3 is a time chart of the above embodiment, and FIG. 4 is a flow chart of the same embodiment. DESCRIPTION OF SYMBOLS 1... CCD sensor, 2... Sample hold circuit, 3... Offset correction circuit, 7... Multiplexer, 8... A/D conversion circuit, 9... Central processing unit, 11° 12.14.15...Analog switch,
16, 17.20... operational amplifier, 18.19...
Sample and hold circuit, 21, 22, 23, 24.25
... constant current circuit, 26 ... comparator, 31 ...
・Offset register. Patent Applicant Asahi Kogaku Kogyo Co., Ltd. Representative Patent Attorney Kunio Miura Procedural Amendment (Automatic 1. Display of Case 1988 Patent Application No. 188763 2 Name of Invention Camera Offset Automatic Correction Circuit Drawing Above and Above Figure 4

Claims (1)

[Claims] (1) A CCD sensor that detects the brightness distribution of the subject, a sample hold circuit that samples and holds the output of this CCD sensor, and a sample hold output, [3v information,
A multiplexer that selects one from AV information and 3V information, and an A/D that converts the output of this multiplexer into Δ/D
converter and a central processor I! that processes the output signal of this A/D converter. I! and a device to output the output of the CCD sensor to A.
In a camera capable of automatic focus adjustment by performing arithmetic processing after /D conversion, an offset register is connected to the output terminal of the sample and hold circuit, and the offset voltage output from the sample and hold circuit is A/D converted. Use the output value to set the value of the offset register,
An automatic offset correction circuit for a camera, characterized in that the offset voltage is corrected by being changed by the central processing unit, and the offset voltage is controlled to a predetermined value. (2. In claim 1, the offset correction circuit includes a plurality of constant current sources whose current values are integer multiples, the same number of analog switches as the constant current sources, and the analog switches. 1. An automatic offset correction circuit for a camera, comprising: an offset register for controlling the offset register.