JPS6081664U - integrated circuit package - Google Patents

integrated circuit package

Info

Publication number
JPS6081664U
JPS6081664U JP1983174577U JP17457783U JPS6081664U JP S6081664 U JPS6081664 U JP S6081664U JP 1983174577 U JP1983174577 U JP 1983174577U JP 17457783 U JP17457783 U JP 17457783U JP S6081664 U JPS6081664 U JP S6081664U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
chips
wiring board
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983174577U
Other languages
Japanese (ja)
Inventor
和泉　孝一郎
高原　正晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1983174577U priority Critical patent/JPS6081664U/en
Publication of JPS6081664U publication Critical patent/JPS6081664U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の集積回路パッケージの一例を示す平面図
、第２図は本考案の一実施例を示す平面、　　図である
。 ｌａ、ｌｂ・・・・・・集積回路素子（チップ）、２・
・・１　　・・・配線基板、３ａ、３ｂ・・・・ｉ・接
続用電極部（パッド）、４　ａ９４　ｂｔ　４　ｃ””
配線導体、５ａ、５ｂｔ５ｃ・・・・・・接続用ボンデ
ィングワイヤ。FIG. 1 is a plan view showing an example of a conventional integrated circuit package, and FIG. 2 is a plan view showing an embodiment of the present invention. la, lb... integrated circuit element (chip), 2.
...1...Wiring board, 3a, 3b...i.Connection electrode part (pad), 4 a94 bt 4 c""
Wiring conductor, 5a, 5bt5c... bonding wire for connection.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のチップを配線基板上に搭載して構成される積項回
路パッケージにおいて、前記チップ間を金属細線により
直接接続したことを特徴とする集積回路パッケージ。1. An integrated circuit package comprising a plurality of chips mounted on a wiring board, wherein the chips are directly connected by thin metal wires.
JP1983174577U 1983-11-11 1983-11-11 integrated circuit package Pending JPS6081664U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983174577U JPS6081664U (en) 1983-11-11 1983-11-11 integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983174577U JPS6081664U (en) 1983-11-11 1983-11-11 integrated circuit package

Publications (1)

Publication Number Publication Date
JPS6081664U true JPS6081664U (en) 1985-06-06

Family

ID=30380025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983174577U Pending JPS6081664U (en) 1983-11-11 1983-11-11 integrated circuit package

Country Status (1)

Country Link
JP (1) JPS6081664U (en)

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