JPS6083295A - Data amplifying circuit - Google Patents

Abstract

PURPOSE:To form a data amplifying circuit capable of high-speed operation by making a fast response to a write signal during writing operation after reading operation. CONSTITUTION:When the write signal is transmitted to I/O bus lines I0 and -I0 after reading operation, a write one-shot signal phiw rises up to a high level, and a node N4 is lowered from the high level to a low level. Therefore, a transistor (TR) Q1 which lowers a common source node N3 to the low potential turns off, and the node N3 enters a low floating state. Therefore, when the write signal of the I/O bus line I0 is the opposite data Low of a read signal and the write signal of the I/O bus line -I0 is the opposite data High of the read signal, the signal High is not led out through a TRQ3 in an on state and the writing speed is not decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (MOS).
,l! The present invention relates to a data amplifier circuit for a dynamometer RAM using ``ET''.

In recent years, one-transistor type MOS dynamic) (, AM
With the increasing size and size, there has been a demand for faster speeds. In order to achieve this speed increase, it is necessary to increase the speed of the data amplifier circuit, which is one of the peripheral circuits of the dynamic AM.

FIG. 1 is a circuit diagram of a conventional data amplifier circuit. The circuit in this figure consists of transistors Q1 to Qso and HWI elements C1 and C2, and is configured to activate the data amplifier (No. 8 φD
1 data amplifier pull-up 1 receives signal φD2, 7''-amplifier reset signal φP and power supply voltage VDD,
- Nuj's 110 pass line I. , ■ 1p is tangent to 0 and becomes 1. Codes N1 to N3 are 1111 points.

Next, the operation of this conventional data amplifier circuit will be explained.

At the time of reset, the data unreset signal φP is used.
h level, and nodes N, , N2 are at High level. In addition, I10 pass line Io,
Io is a 110 bus precharge transistor (not shown) K, 1: ! 1M7'C to 7171-1i level
and the node N3 is lower than the gh level of the transistor Q.
The voltage is lower by VT (threshold voltage) of ztQa. Signal φD! , φDtfiLow level. At the time of starting, φP goes to low level and the pair of I10 bus lines. , Eng. The resistance signal is transmitted to , the data amplifier activation signal φDl rises to High level, and the common source node N3 of transistors (h, Qs) is lowered to Low level, and the signals of ■., G are amplified. Considering the case where the s IO signal is 14 i g h and the ■. signal is Low, transistor Q3 is turned on.
Since the transistor Q2 is in the OFF state, only the 1-1 i g h level on the G side is dropped, and the high level of the node N2 is lowered to the low level via the transistor Qs. After that, when the data amplifier pull-up signal φD rises to High level,
The level of the node N1 is raised by the capacitive element CI, and the transistor Q6 is turned on. High side level compensation is performed.

The above is an explanation of the operation at the time of reading. After reading, this data amplifier circuit performs 1/(J-<sline ■.

C has a drawback that when a write signal having data opposite to the read signal is transmitted, a response to the write signal cannot be made quickly. In other words, the sIO indulgence signal is High. The write signal is low.

Considering the case, when hv is output, transistor Qt is in the OFF state and transistor Q3 is in the ON state, so Q
s is ■10 pass line I. The canceling force continues until the Low write signal of line I turns off the transistor Q3.

As described above, the data amplifier circuit shown in FIG. 1 has the disadvantage that it cannot operate at a sufficiently high speed because it operates to slow down the write speed during one write after reading.

An object of the present invention is to provide a data amplifier circuit that can operate at high speed using t5Ti.

The configuration of the present invention includes a pair of field effect transistors whose drains and gates are cross-connected and whose source is common;
The pair of '#lt,'! 1--A data amplifier circuit comprising means for pulling the saw 2 to a low potential when a read signal is transmitted to a pair of 110 pass lines, each connected to a drain of an effect transistor, wherein the pair of I10 buses are connected to the After the Lc output signal is transmitted and the source is pulled to a low potential, and when or before a write signal is transmitted to the I10 pass line, the source is brought into a floating state. Features.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of an embodiment of Genmei. This implementation 1
y (1 is the transistor Q I-Q 10 and Q 21
~Q consists of snow s and valley element CII z C12, and data amplifier activation signal φDl+data amplifier up signal φ.

Data amplifier reset signal φ2. Upon receiving the write one-shot signal φ and the pressure VDD, the pair of
C) Pass line 1° and ■. , is connected to.

Next, I will explain the IJ operation of this implementation column.At the time of reset,
When outputting Φ, the operation is explained in the conventional relay in Fig. 1, and the write one-shot signal φ remains at a low level, and the gate node N4 of transistor Q1 is as explained in the conventional relay. The data amplifier activation signal φ is rotated.
I'll omit the explanation since it's complete. Therefore, the case where writing is performed after one pile is taken out will be explained. I10 after resistance
Pass line■. FIJe, output signal is High, I
10 pass line■. When the write signal of VC is Low, as explained in the conventional example, transistor Q1 is Off+.
In the 1111 state, the transistor Q3 is in the ON state. I
10 pass line■. When a one-way signal is transmitted to +'O, the write-one/yacht signal φW rises to the Ihigh level, and the node N4 is pulled from the lligb level to the Low level. Therefore, transistor Q1, which pulls common source node N3 low, is OF
The state is F, and the i'Irj point N3 is in the l,ow floating state. Therefore, the following is the path line. Input (, (number is 1, the data is opposite to the outgoing signal,
Low, 1/(J pass line ■.) When the sneak signal is High, which is the opposite data to the read signal, the High signal is not pulled out via the transistor Q3 which is in the ON state, and the speed when sinking is slow. As mentioned above, the data amplifier circuit of the present invention quickly responds to the 1-pruning signal at the time of 1-cutting after reading. Therefore, according to the present invention, the high-speed operation is 5h for data exceeding 4. Amplifier circuits can be provided.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Qs-Q+o+ Q21-Q21""") transistor,
C1゜C2...,...Answer 2. element, φ0.・・・・・・
...Theta amplifier activity ratio signal, φD, ...- Data amplifier pull-up No. 11M, φP... Data assembly reset signal, φW... Write one-shot signal, ~'DD... ...Width, W6 pressure, '01'o...
...1/(J pass line, 1'J, ~N4°°゛°°
node.

Claims (1)

[Claims] When a read signal is transmitted to a pair of field effect transistors whose drains and gates are cross-connected and whose sources are common, and a pair of I10 pass lines each connected to the drains of the pair of field effect transistors, ni1i
In the data amplifier circuit having means for pulling the J source to a low potential, the +4:I
Note: After the output signal is transmitted and the source is pulled to a low potential, when an additional signal is transmitted to the j10 pass line, or when this transmission occurs, the +iiJ source is in a bad loading condition. A data amplifier circuit characterized in that it has means for.