JPS6084876A - Manufacture of power transistor - Google Patents

Abstract

PURPOSE:To improve the yield by preventing the generation of warps and the like of a semiconductor substrate by a method wherein, using a semiconductor substrate of a large plate thickness, an emitter layer, a base layer, and a collector layer are formed, and an emitter electrode and a base electrode are formed on the surface side of the substrate; thereafter the back of the substrate is cut. CONSTITUTION:Preparing a thick power transistor Si wafer 3 having an N<-> layer 1 and an N<+> layer 2, the emitter layer 5 and the base layer 6 are formed. At this time, an N<++> layer 9 is formed by impurity diffusion to the back of the Si substrate 3 at a high concentration at the same time. Next, after the emitter electrode 5a and the base electrode 6a are formed in the emitter layer 5 and the base layer 6, respectively, the back side of the wafer is cut by grinding, resulting in the reduction of the thickness of the wafer. A high concentration impurity layer 10 is formed by doping of the impurity at a high concentration to the N<+> layer 2 on the back side of this wafer by the use of an ion implantator. When the impurity ions are activated on low temperature annealing by laser annealing, the impurity layer 10 is activated, and the electric characteristic of contact with the electrode metal improves.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a power transistor.

[Background technology]

Generally speaking, silicon wafers with a thickness of 300 to 500 microns are used for transistors. However, silicon wafers that are particularly thin are used for power transistors. This is to lower the switching resistance of the power transistor and reduce power loss. A silicon wafer for such a power transistor is shown in FIG. In the figure, 1 is an N single layer (low impurity concentration: high resistance), and 2 is an N+ layer (high impurity concentration: low resistance). In this case, the impurity concentration of the N+ layer 4 is about l Q '' cm-3. By using such a thin silicon wafer 3 and passing it through the power transistor process, the structure shown in FIG. 2 is obtained. A power transistor 4 as shown in FIG. 2 is obtained.
5 is an emitter layer, 6 is a base layer, and 7 is a collector layer. The emitter layer 5 is provided with an emitter electrode 5a, and the base layer 6 is provided with a base electrode 6a. Further, the front surface of the silicon wafer 3 is covered with an oxide film 8, and a N layer 9 is formed on the back surface.

The N'' layer 9 on the back surface is a layer with a high impurity concentration provided to lower the contact potential difference with the collector electrode metal provided on the back surface and the switching resistance of the transistor, and the impurity concentration is lQ'' cm- It is set to about 3. Note that since this N'' layer 9 is formed at the same time as the emitter layer 5, the impurity concentration of the N'' layer 9 and the impurity concentration of the emitter layer 5 are the same.

However, when manufacturing the power transistor 4 in this way, since the silicon wafer 3 is thin,
Problems have arisen in that wafers may be damaged due to handling during the transistor manufacturing process, and wafers may be warped due to heat, resulting in poor yields. Therefore, a method has been devised in which a thick silicon wafer is used instead of the thin silicon wafer 3, this is passed through the transistor manufacturing process, and the thickness of the silicon wafer 3 is finally reduced by polishing. That is, as shown in FIG. 3, an emitter layer 5 and a base layer 6 are formed on a thick silicon wafer 3 having one layer of N and two layers of N''''.
In addition to forming electrodes 5a and 6a, respectively, a N layer 9 is formed on the back surface of the silicon wafer 3. In this case, the formation of the N layer 9 is performed simultaneously with the impurity diffusion of the emitter layer 5, and its concentration is 1020a11 as described above.
Next, the back side of this silicon wafer 3 is ground down as shown in Fig. 4, and the thickness is reduced to 200 to 250μ.However, the thickness is reduced in this way. In this case, the Jim (N'' layer) with high impurity concentration provided on the back side of the silicon wafer 3
9 is removed, and the N3 layer (impurity concentration 1018c "3) 2" with a low impurity concentration inside it is exposed. However, this N"N2 has a low impurity concentration, so When forming a collector electrode in a transistor, a problem arises in that the contact potential difference with the electrode metal increases and the switching resistance of the transistor increases. Furthermore, depending on the type of electrode metal provided on the back surface, even if the electrode metal is vapor-deposited on the back surface side of the silicon wafer 3, there may be a gap between the vapor-deposited electrode metal and the back surface side portion of the silicon wafer 3. As shown by the broken line curve A in FIG. 5, ohmic contact may not be established. Furthermore, the fifth
In the figure, straight line B indicates a state where ohmic contact is established.

[Purpose of the invention]

The purpose of the present invention is to improve the yield by preventing the occurrence of warping of the semiconductor substrate during the manufacturing process without deteriorating the contact electrical characteristics between the back surface of the semiconductor substrate and the electrode metal. be.

[Disclosure of the invention]

The present invention includes a step of preparing a thick semiconductor substrate on which an emitter layer, a base layer, and a collector layer are formed, a step of forming an emitter electrode and a base electrode on the front side of the semiconductor substrate, and a step of forming an emitter electrode and a base electrode on the front side of the semiconductor substrate. After forming the base electrode, the back surface of the semiconductor substrate is cut to reduce the thickness of the semiconductor substrate, the back surface of the cut substrate is ion-implanted to form a high concentration impurity layer, and the formed high The gist thereof is a method for manufacturing a power transistor characterized by comprising a step of activating a layer of concentrated impurities.

That is, this invention uses a thick semiconductor substrate,
This is applied to the transistor manufacturing process, and in the final process, the back side of the semiconductor substrate is polished to reduce its thickness, and then a highly concentrated impurity layer is formed by ion implantation, and then the layer is activated. An activated high-concentration impurity layer is formed on the back side of the substrate, thereby improving the electrical characteristics of the contact between the back side of the semiconductor substrate and the electrode metal. In addition, 1. By using a thick semiconductor substrate, the occurrence of warping of the semiconductor substrate during the manufacturing process can be prevented, and the yield can be improved.

Next, the present invention will be explained in detail based on examples.

That is, as shown in FIG. 6, N1 layer 1 and N'''''' layer 2
A thick silicon wafer 3 for a power transistor is prepared. Next, this silicon wafer 3 is subjected to the same processing as in the conventional example to form an emitter layer 5 and a base layer 6, as shown in FIG. This emitter layer 5
At the same time, an N++ layer (10''c13) 9 is formed by diffusing impurities at a high concentration on the back surface of the silicon substrate 3.

Next, emitter electrode 5a and base electrode 6a are formed on emitter layer 5 and base layer 6, respectively. 8 is an oxide film. Next, the back side of the silicon wafer 3 treated as described above is cut by polishing to reduce the thickness of the silicon wafer 3 as shown in FIG. When the thickness of the silicon wafer 3 is reduced in this way, an NI layer (101
8cm-3)2 is now exposed, the N0 layer 2 on the back side of the silicon wafer 3 is doped with impurities at a high concentration using an ion implanter as shown in FIG. Form IO. In this case, the impurity concentration of the high concentration impurity layer 10 is set to about 10" cm-3. However, if the high concentration impurity layer 10 is simply formed on the back side of the silicon wafer 3, impurity ions will not be generated. Since it is inert, impurity ions are activated by low-temperature laser annealing.As a result,
As shown in FIG. 10, the highly concentrated impurity layer IO on the back side of the silicon wafer 3 is activated, and when a collector electrode is provided, the contact electrical characteristics with the electrode metal can be improved. Moreover, ohmic contact can be made as shown by straight line B in FIG. 5 regardless of the type of electrode metal.

〔Effect of the invention〕

As described above, the present invention uses a thick semiconductor substrate, subjects it to a transistor manufacturing process to form an emitter layer, a base layer, and a collector layer, and forms an emitter electrode and a base electrode on the front side of the semiconductor substrate. Since the back side of the semiconductor substrate is cut to reduce the thickness of the substrate, the semiconductor substrate will not be damaged by handling during the transistor manufacturing process, and there will be no problems such as warping due to heat, improving yields. do. After cutting the back surface in this way, a high concentration impurity layer is formed and activated by ion implantation on the back surface of the cut substrate, so when providing an electrode metal on the back surface of the semiconductor substrate, the electrode metal is Good electrical characteristics of contact with the semiconductor substrate can be maintained.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams for manufacturing a power transistor, FIGS. 3 and 4 are explanatory diagrams of improved examples thereof, and FIG. 5 is a voltage-current characteristic diagram for explaining an ohmic contact.
FIGS. 6 to 10 are explanatory views of manufacturing an embodiment of the present invention. 3... Silicon wafer 5... Emitter layer 5a.
...Emitter electrode 6...Base layer 6a...Base electrode 7...Collector layer 10...High concentration impurity layer Agent Patent attorney Takehiko Matsumoto

Claims (1)

[Claims] (1) A step of preparing a thick semiconductor substrate on which an emitter layer, a base layer, and a collector layer are formed, a step of forming an emitter electrode and a base electrode on the front side of this semiconductor substrate, and a step of forming an emitter electrode and a base electrode on the front side of the semiconductor substrate. After forming the electrodes, the back surface of the semiconductor substrate is cut to reduce the thickness of the semiconductor substrate, and the back surface of the cut substrate is ion-implanted to form a layer of high concentration impurities. A method for manufacturing a power transistor characterized by comprising a step of activating an impurity layer.