JPS608635B2 - field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor, and more particularly to a field effect transistor for obtaining a high diode breakdown voltage.

A drawback of conventional field effect transistors is that the shorter the source-drain interval, that is, the channel length, the lower the drain breakdown voltage in absolute value.

This phenomenon is generally called a punch-through phenomenon, and is caused by a depletion layer extending from the drain region toward the source region reaching the source region due to a zero voltage applied to the drain. In addition, the drain breakdown voltage has dependence on the composition, structure, and thickness of the gate insulating layer, and the thicker the gate insulating layer, the higher the drain breakdown voltage in absolute value. It is known that when the membrane has a two-layer structure, the drain breakdown voltage exhibits a high absolute value.

In recent years, field effect semiconductor devices have become highly integrated, and as a result, field effect transistors used as internal elements have also become smaller, and the spacing between the source and drain, that is, the channel length, is also becoming narrower. The above-mentioned punch-through phenomenon is a problem in field effect transistors with such narrow channel lengths, and is currently hindering the increase in the degree of integration of field effect semiconductor devices.

As mentioned above, the drain breakdown voltage has two different modes; one is limited by the punch-through phenomenon, and the other is limited by the composition, structure, and thickness of the gate insulating layer. mode.

Since the latter is inevitably determined by the composition, structure, and thickness of the gate insulating layer of the field effect transistor, the former punch is more important in field effect transistors used in actual highly integrated field effect semiconductor devices. It is clear that modes that are restricted by the through phenomenon are important.

As a result of selecting several types of gate insulating layers and measuring their drain breakdown voltages, we discovered a new phenomenon. The thickness of the gate insulating layer is 300A or more, which is a thin insulating layer that is normally used.
A total of nine types of insulating layers, including seven types at intervals of 500 A up to 3300 A and two types of thick insulating layer thicknesses of 6000 A and 11000 A, were formed by heat treatment in a wet oxygen atmosphere at 1140 am.

Regarding the manufacturing method of this field effect transistor, the first
This will be explained with reference to the figure.

The semiconductor substrate 1 used has a crystal orientation (511) and a resistivity of 4.
．． 50 N type single crystal silicon, 1140℃,
An oxide film 2 of approximately 5000 Δ is formed by heat treatment in a wet oxygen atmosphere, and a first pore process is performed to selectively form source and drain regions [a)].

Next, in a 105,000 impurity diffusion furnace, a P-type impurity diffusion layer 3 that will become a source and drain is formed, and then 114
The insulating layers 2' and 2'' are formed by pressing in a dry oxygen atmosphere at 0° C. and then by vapor phase growth.The insulating layer 2' is usually called a field insulating layer [b)].
Next, a second hole opening process is performed to selectively open holes in the gate region, and the skin of the gate insulating layer 2 described above is formed [c
)]. Subsequently, a third hole-opening process is performed to create lead-out electrodes from the source and drain, and the gate electrode and lead-out electrode 4 are formed [d]. As a result of measuring the drain breakdown voltage of the field effect transistor manufactured using the above process, it was found that as the gate oxide film becomes thicker, the absolute value of the drain breakdown voltage, which is limited by the punch-through phenomenon, decreases.

Note that the drain breakdown voltage, which is limited by the thickness of the gate oxide film, is contrary to the drain breakdown voltage which is limited by the punch-through phenomenon, and as is known, the thicker the gate oxide film, the higher the absolute value becomes. It has been found that this tendency does not change even if the composition and structure of the gate insulating layer is changed, or even in an N-channel type using a P-type semiconductor substrate. There are two modes of drain breakdown voltage as described above, the first mode is limited by the composition, structure, and thickness of the gate insulating layer, and the second mode is limited by the punch-through phenomenon.

Regarding the former, the 32nd Academic Conference of the Japan Society of Applied Physics (19
(1971), and the theoretical explanation will be omitted here. Next, we will provide a theoretical explanation of the latter. Normally, drain breakdown voltage measurements are performed by applying a voltage to the drain and setting the gate, source, and semiconductor substrate to fog potential.

The electric field applied to the drain is therefore split into an electric field reaching the gate electrode through the gate insulating layer and an electric field reaching the source through the channel region. Therefore, if the gate insulating layer becomes thicker, the electric field that reaches the gate electrode through the gate insulating layer becomes smaller, and the electric field that reaches the source through the channel region becomes larger, which increases the extension of the depletion layer from the drain to the source, resulting in the punch-through phenomenon. This can be explained by the fact that this is more likely to occur.An object of the present invention is to provide a field effect transistor that is effective for improving drain breakdown voltage.

According to the present invention, it is possible to obtain a field effect transistor that can obtain a desired drain breakdown voltage, that is, a drain breakdown voltage value that is limited by the composition, structure, and thickness of the gate insulating layer, even in a transistor with a short source-drain distance, that is, a short channel length. It is characterized by being

The present invention will be described in detail below with reference to the drawings.

Figures 2 to 4 show part of the plan view of a conventional field effect transistor. There is a region with a thick insulating layer 2'. More specifically, in FIG. 2, regions 6 and 6' are formed near the source and drain hole regions 5 and 5' by pushing impurities, and a depletion layer 7 is formed further outside the drain hole region 5'. is expanding and existing. Furthermore, two gate insulating films are provided between the source G drain opening regions 5 and 5', and the ends of the two gate insulating films are located inside the channel, not at the ends of the source mountain and drain opening regions 5 and 5'. It is sewn with Therefore, the end of the gate insulating layer 2 and the source. Drain opening area 5, 5' between ends and area 6, 6 by pushing
Naturally, there is a thick field insulating film 2' between the two regions.
In addition, in FIG. 3, source/drain opening regions 5,
Between 5' and 5', there are two gate insulating films up to the end, but the source is still effectively pushed in. A thick field insulating film is present at the end between the drain impurity diffusion regions 6, 6'. In FIG. 4, the gate film 2 is provided so as to cover the ends of the source/drain impurity diffusion regions 6, 6' by pressing, but the gate film 2 is provided so as to cover the tip of the depletion layer 7 of the drain region 6'. It is not set up.

In this way, in the conventional transistors shown in FIGS. 2 to 4, a field effect transistor has two gate insulating layers, that is, a thin insulating layer in the channel region, and a field effect transistor has a field insulating layer 2', that is, a thick insulating layer. This is equivalent to effect transistors connected in parallel, and a punch-through phenomenon occurs outside the field effect transistor having a field insulating layer, resulting in a drain breakdown voltage that becomes low in absolute value.

The shape of the field effect transistor of the present invention is shown in FIG. 5 and FIG.
Needless to say, the extension of the depletion layer 7 due to the voltage applied to the drain is also considered, and there is no field insulating layer within the entire effective channel area, and the composition, structure, and thickness of the gate insulating layer are A desired drain breakdown voltage can be obtained, which is subject to limitations.

Currently, the absolute value of the maximum voltage used in field effect transistors or field effect semiconductor devices using field effect transistors is around 30 (V) to 40 (V), and if the effective channel length is 7 meters or more, Since the drain breakdown voltage, which is limited by the punch-through phenomenon, is higher in absolute value than the drain breakdown voltage, which is limited by the composition, structure, and thickness of the gate insulating layer, the present invention is very effective when the effective channel length is less than 7 meters. It turns out that.

[Brief Description of the Drawings] Figures 1a to d are diagrams showing a general manufacturing method of field effect transistors, Figures 2 to 4 are plan views showing the shapes of subordinate transistors, and Figure 5 , FIG. 6 is a plan view showing an embodiment of the present invention. Explanation of symbols, 1... Semiconductor substrate, 2, 2''...
...Insulating layer, 2'...Field insulating layer, 2 rivers...Gate insulating layer, 3...Impurity diffusion layer, 4...Extracting electrode and gate electrode, 5,
5'... Source and drain regions having the shape immediately after the hole step, 6, 6'... Expanding portions of the source and drain impurity diffusion layers due to pushing, 7...
...Depletion layer expanded by drain applied voltage. Figure 1: Hair 2: Figure 3: Hair 4: Hair drawing

Claims (1)

[Claims] 1. In a field effect transistor in which a depletion layer is generated in the vicinity of the drain region due to a voltage applied to the drain region, a gate insulating film is provided to cover at least the entire effective channel region formed by the depletion layer, or the gate insulating film is generally referred to as the gate insulating film. A field effect transistor characterized by having insulating films having the same thickness and the same composition.