JPS6090430A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the probability of error correction by counting error-corrected bits and handling data as the erroneously detected data regardless of the contents of a syndrome register when the counted value is large. CONSTITUTION:A CPU leads data 113 before error correction to a data register 103 and the syndrome register 109 through a parallel-serial converting circuit 101. A majority decision circuit 110 operates on the basis of a threshold value in response to an error correction gate signal 123 to output an error correction signal. An error correction signal 124 generated by the syndrome register 109 during majority decision difference set cyclic code error decoding operation is counted by the counter in an error detecting circuit 111, and an error uncorrectable state signal 131 is outputted once the counted value attains to ''13'', so that an error status signal 118 displays error detection all the time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection circuit for character code broadcasting that transmits digitally coded character information during the vertical retrace period of a television signal and displays it on a home television receiver or the like. It is.

Conventionally, in Japanese character code broadcasting, it has been considered best to use the (272,190) code as an error correction method. This is reflected in the patent application filed in 1985-85 by the present applicant.
This is clear from No. 78 "Error Correction Decoding System". In other words, this application relates to an error correction decoding system that attempts to recover as much as possible by correcting bit errors occurring in a transmission path, in which data bits 273 . Using a signal of 191 information bits and 82 bits of attribute bits, one bit is reduced from this signal to configure one packet of 272 bits, and data bits 272. By forming and transmitting a data signal of 119Q information bits and 82 bits of normality bits, and multiplying the transmitted data signal by a matrix of predetermined columns and all 1, the error correction probability is increased and the information is The purpose is to be able to decrypt .

Using the basic error correction decoding method proposed in a series of patent applications 1985-8579~), one packet (27
Although it is possible to correct errors of 8 bits (2 bits), it is almost impossible to correct errors of 9 bits or more.

Another improved error correction decoding method proposed in the above-mentioned application (i.e., a method that can correct errors of 9 bits or more by shifting the leading bit when the error cannot be corrected) ) had the disadvantage that the processing time was too long.

Therefore, 4, -m1 Sho 58-54002 by the present applicant
No. 1 describes a syndrome register, a majority decision circuit that uses a majority difference set cyclic code in order to improve the error correction ability and reduce processing time at the same time.

Errors involving data registers, + [In the correct decoding system, a subtraction circuit is added to the majority decision circuit, the decision threshold of the majority decision circuit is set to a specific value within the number of input elements of the majority decision circuit, and after cyclic correction, the subtraction circuit The gist is to sequentially subtract a specific number from the judgment dark value via , reduce the judgment threshold value until it reaches a predetermined value, and perform corrective decoding.

However, all of the above-mentioned methods have the drawback of causing undetectable errors.

In view of the above-mentioned points, an object of the present invention is to reduce the probability of error correction by treating it as error detection when the number of error correction bits is large even when error correction detection in character code broadcasting is impossible. An object of the present invention is to provide an error detection circuit.

In order to achieve such an object, the present invention counts the number of error correction bits generated from a syndrome register during cyclic correction in an error correction circuit for character code broadcasting using a majority-set cyclic code error decoding power formula. However, when the count value reaches a specific value or more, a means is provided to determine that an error has been detected even if all the syndrome registers are zero, thereby reducing typographical errors.

The present invention will be described in detail below with reference to the drawings.

First, regarding the first embodiment of the present invention, FIGS.
This will be explained with reference to the figures.

Here, FIG. 1 shows an embodiment of an error detection circuit to which the present invention is applied.

FIG. 2 is a simulation diagram showing the difference in correction F ability based on the initial threshold 1i when correction is performed by sequentially lowering the threshold. Here, the sentence is the initial threshold of the majority logic.

FIG. 3 is a flowchart showing the entire control procedure in the first embodiment of the present invention. Here, the steps shown here are steps that indicate the operation of the CPU.6 In other steps, the circuit operates automatically. Note that each step shown in the diagram is described in 1. in the explanation of FIG. 1 below. I will also mention this.

In the first UA, +00 is the output port of the central processing unit CPυ (not shown), and 101 is the forward direction (P/S)/plane difference (
S/P) conversion circuit, 102 is a selector, 103 is a data register (272 bits), 104 is an adder modulo 2, 105 is CPU (7) input capo), 10Ei is a gate, 107 is a modulo 2 108 is a timing generator, 109 is a syndrome register (82
110 is a majority logic circuit, ll is an error detection circuit, 112 is a clock 4g, 113 is data before error correction, 114 is data after error correction, 115 is a reset signal, 118 is a load signal, 11? is the fetch signal,
118 is an error status signal, 118 is a ready signal,
120 is a data load control signal, 121 is a data load pulse signal, 122 is a data load clock signal, 12
3 is an error correction gate signal, 124 is an error correction signal, 12
5 is the syndrome shift crofter signal, 126 is the Hue・
Clock signal for Sochi, 127 is serial load data,
Reference numeral 128 indicates circular data, 128 a syndrome register signal, 130 a threshold reduction signal, and 131 an error correction uncorrectable signal.

When the CPU receives the packet y l signal, it begins error correction processing for that packet y l signal.゛First, the reset I signal 115 is issued, and the syndrome register 109 (7)
All 82 bits are set to 0''', the timing generator 108 is set to the initial state i, the threshold value of the majority logic circuit 110 is set to the initial state 17, and the error detection circuit 1
] Set the imposition correction counter of 1 to °°0°', respectively.
and prepare for data loading.

Next, the CPU loads the received packet signal (ie, data before error correction +13) to the parallel-to-serial conversion circuit 101. When this conversion circuit 101 is for 8 pictographs, 34 times,
If it is for 1θ bit, it will be loaded only 17 times. The load timing is performed in response to the load signal 116.

When the timing generator 108 receives the load signal 11[1, it issues a data load pulse signal 121, transfers the data 113 before error correction to the register of the conversion circuit 101, and in response to the data load clock signal 122, outputs the data 113 to the conversion circuit. 101 data to data register 103
and leads to the syndrome register 109. At this time, the data load control signal 120 controls the gate 106 to pass the serial load data 127, and the data selector 102 controls the serial load data 127.
is the mode to select. Of course, when the conversion circuit 101 is 8 bits, the number of pulses of the load clock signal is 8.
When the conversion circuit 101 is 18 bits, the number of pulses of the load clock signal is 18 bits. At this time of loading, the majority logic circuit 11 (l) is inhibited by the error correction gate signal 123, and the error correction signal 124 is not output.

Once all data is loaded into data register 103 and syndrome register 108, the circuit automatically enters error correction operation. At the first time, in response to the control error signal (error correction gate signal) 123, the majority circuit 110 operates according to the threshold value "1?", and the so-called correction signal 124 is activated.
Output. If there is no error at all from the beginning, the error detection circuit 111 detects no error from the syndrome register signal 12+1 by the logical sum thereof, and does not enter the error correction operation.

The CPU sees the error status 2740 No. 118 and knows that there is no error, and decodes it using the received packet signal in the CPU as it is.

A clock signal during error correction is provided by data load clock signal 122. When a 272-bit clock signal is output for one cycle, only the syndrome register lo8 is shifted by 1 bit by the 1-bit clock of the syndrome shift clock I-1 125. At this time, the error correction gate signal 123 is turned off,
No error correction is performed. The reason for this is that the period of the syndrome is 273 degrees, which is different from the period of data 272 degrees. If all the errors have been corrected in this one cycle, the error status signal 118 indicates no error, and the ready signal +19 prompts the CPU to complete the data processing. Therefore, the CPU only needs to constantly monitor the ready signal 119. Alternatively, the ready signal 119 may be supplied to the interrupt control line to notify the CPU.

The error-corrected data that has passed through the adder 104 modulo 2 (
The circular data) 128' is loaded and sold again to the data register IO3 via the data selector +02. Further, the error detection circuit 111 includes a counter that counts the error correction signal 124, and is configured to output an error 311F disable signal 131 when the counter indicates '13'. When signal 131 is being sent.

The error status signal 118 is also configured to always indicate an error detection.

The timing generator 108 that has received the error uncorrectable signal 131 outputs a ready signal 11θ at the point where one round of bit shifting is completed.

The CPU attempts to take in data, but upon seeing the error status signal 118, it learns that there is an error, and decides not to use that packet.

When error correction by one round of data shifting is not completed (that is, all of the syndrome registers 108 are
When the timing generator 1 is not 0° or the error correction signal is not output 12 times or more,
By subtracting the threshold value from No. 48 130, the threshold value of the majority logic circuit 110 is set to -1", that is, "'16".
Perform the same operation as last time. By repeating such circuit operations, if error correction cannot be completely performed on the way, the threshold value is successively lowered until the calculation of the original threshold value ゛9°゛ is completed. If the error status signal 118 does not indicate no error at this point, an error has been detected and this data is not used. At this time, the ready signal 11f3 and the error status signal 11
8 notifies the CPU of the error detection.

If the error correction ends midway (that is, when all the syndrome registers are '0' and the error correction signal is output 12 times or less), the threshold value of 27
2 At the same time as the end of the bit shift I, the ready signal 119 is output, and the error status signal 118 notifies the GPU that all III has been stopped.The count number of the error correction signal is fixed at 12" and used for error detection. The reason is that in the method of correcting errors by lowering the threshold one by one,
This is because error correction of IO bits or less is possible in almost all cases, and 90% of errors of 11 bits can be corrected. Figure 2 shows the results of the total XS simulation.

At the end of error correction (i.e. syndrome register 10
9 are all "0"', and the error correction count number is °'1
1” or less), the CPU issues a fetch signal,
Start importing data after error correction. Depending on the fetch signal, the ready signal 119 temporarily indicates a busy state, but
When data is set in the surface difference conversion circuit 101, the ready signal 119 is displayed again. Seeing this ready signal 119, the CPU takes in the data from the conversion circuit 101. Since the required data has a length of 190 bits, fetch signals will be generated 24 times for fetching every 8 bits and 12 times for fetching every 18 bits. C
After taking in 180 bits of data, the PU interprets and displays the data, and then begins the next packet reception process.

The above is an explanation of the operation of the first embodiment of the present invention.

Next, a second embodiment of the present invention will be described.

In the first embodiment described above, the syndrome register 109 determines whether or not the error correction has been performed correctly.
Although this was done only when the error correction count number was 11' or less, the probability of correctly correcting and restoring the packet signal could be increased by increasing the so-called limit on the count number or changing the number of errors. However,
In this case, feg<, which is erroneously restored, will also increase, so
CRC (Cyclic Redundancy C1r)
eck)'s error detection function in the data section will give you peace of mind.

FIG. 4 shows a second embodiment of the error detection circuit according to the present invention. Here, 400 is an encoder, 401 is a counter from t, 402 is a comparator, 4o3 is an OR circuit, 4
04 is a signal from a push button switch (not shown) indicating °'11'', 4o5.aoe, ao7 are respectively °
Signals from the push-button switch indicating "12°',""13", and "+4"; 408 is a signal from the push-button switch indicating no limit; 408 is the signal 1 shown in the first diagram.
15 is the same reset signal, 41O is the signal 12 shown in the first diagram.
The same error correction signals as 4, 411-414 are the numbers 404-40? to the push buttons mentioned above. encoded signal, 41
5 is the output signal of the counter 401, 41J is the signal 1 in Fig. 1
31) is an error detection signal based on the number of error corrections, 417 is the first
The illustrated signal 128 represents the error detection signal from the syndrome register.

Push button signals 404~ by an external switch
408 is "1", which specifies the threshold level for determining error detection.For example, if the push button signal 404 is "'l" tt i
”+lf, encoded signal 4 passed through encoder 40θ
11 to 414 represent °"11''. That is, the signal 411 is "l'", the signal 412 is °°1°°, and the signal 41 is "l'".
The encoded signals 411 to 414 become one input signal of the comparator 402.

408 is a reset signal, which is output at the start of error correction. This reset item ) 409 is the counter 401
Set to the initial state of °゛O゛. In this state, when the packet signal 19 (19) is entered into a correction operation, a counter input signal (that is, an error correction signal) arrives to perform error correction, and the counter 401 is counted and amplified. The comparator output signal 16 becomes l' when it becomes larger than Wi specified in 411 to 414.

Also, the error detection signal 41? from the syndrome register?
Even if the current value is 0° (that is, when the syndrome register is 0°), the comparator output No. 1 41G that has passed through the OR circuit 403 remains unchanged and outputs 1°' to the error status signal 118. This appears as 1, indicating error detection.

If the push button signal 40B indicating no limit is °'1', 1. 'ii! stop the detection function. That is, one value of the input to the comparator 402 is set to a value exceeding 272°, or the output signal 41B of the comparator 402 is directly controlled so as not to become "1". error correction circuit (for example, the above-mentioned patent application No. 58-5400)
The same operation as (see No. 2) is also possible. In this case, the probability of error correction increases, but naturally the probability of error correction also increases. Therefore, the error detection function using CRC in the main text becomes even more important.

In the above explanation, we took the method of changing the designated numbers of the push button signals 404 to 407 from °'11" to °1+Il+,
Similarly, °+2°“ I+ +311, 1+ +41
1. ...and set the specified number to 5 instead of 4.
Of course, the same functionality can be obtained even if the number is specified as more than or equal to three or less. In addition, the push button signal 40
It goes without saying that the same effect can be obtained even if the configuration is such that the designation of 4 to 408 can be commanded from the CPU.

Furthermore, an ff4J3 embodiment of the present invention will be described.

In the second embodiment described above, the same effect can be obtained even if the error detection signals 416 and 417 are provided as separate flags and the CPU is notified of each. C.P.
On the U side, only the error detection signal 417 from the syndrome register is used for error detection, or
Whether or not to include the information of the error detection signal 416 based on the number of error corrections in determining error detection can be selected by the user's program.

@Later, the fourth aspect of the present invention will be explained regarding the downstream side.

In the third embodiment described above, by configuring the output data of the counter 401 to be directly decoded on the CPU side instead of the error detection signal 416, the error-corrected data can be used once. Software can determine whether to use it or not. In the case of framing timing detection as shown in Japanese Patent Application No. 58-180523 filed by the present applicant.

Judgment should be made by changing the threshold level from when detecting an error in a normal packet signal, but in this case as well, the CPU
By simply reading the count number, together with the error detection signal 417, it is possible to determine whether the framing timing is correct or not using a program. In this case, as a matter of course, no comparison is performed by the comparator, so error correction is performed until the end (that is, up to the threshold value "9"). Furthermore, by constantly counting and managing the error detection rate using software, it is possible to control the error detection threshold level and thereby keep the error correction rate constant to some extent regardless of the reception environment. Furthermore, there is an advantage that the information on the error correction count number can be used as feedback information for the slice level adjustment, sample phase adjustment, and waveform equalization amount of the signal identification circuit in the character code broadcast receiving apparatus.

Each of the embodiments described above is based on the error correction circuit shown in the previously mentioned Japanese Patent Application No. 58-54002, so the initial threshold level (fj of the majority circuit) is
Instead, a correction effect similar to that of Habo can be obtained13
Even if the variable level of threshold 1'1^ is set to "-2°" or "-3°" instead of "-1".

Even if set to It is also possible to obtain error correction effects similar to Habo.

As described in detail above, by implementing the present invention, it is possible to obtain an overview of the count number of error correction bits, and therefore it is possible to achieve the effect of reducing the probability of error correction.

Next, the effects of each example will be listed.

In the i1 embodiment, error detection from the syndrome register and 1. ; Since the logical sum with the error detection by counting the serial correction bits is calculated and the result is notified to the CPU as a flag, there is an advantage that the circuit and program can be easily configured.

In the second embodiment, the threshold value of the counter output of the error correction bit in the first embodiment is made variable and an external force is applied.

Alternatively, it may be specified by the CPU, so that the threshold number ipo1 of the error correction bit count is increased at points with poor reception conditions. This makes it possible to greatly increase the reception probability at points with poor reception conditions.

In the third embodiment, error detection from the syndrome register and error detection by counting error correction bits are notified to the CPU as separate flags, and the CPU makes the determination of error detection. and,
Depending on the purpose of use, it is also possible to ignore error detection by counting error correction bits.

In the fourth embodiment, the CPU is configured to directly read the counter output indicating the count number of error correction bits, and the threshold value for error detection is determined by software. Further, information on the error correction count number can be input to the signal identification circuit and the waveform equalization amount. In this case, it is not necessary to directly specify the threshold value using a push button or to specify the threshold value from the CPU as one input to the comparator. If this comparison input is manually input as a status signal to the CPU,
By comparing with the counter output by software, it is also possible to adopt a configuration similar to that of the first to third embodiments.
It is Ding Noh.

As explained above, in the present invention, when the number of error correction bits is counted and there are many callans +-a, even if the contents of the syndrome register are all °゛0°', one error detection is performed. This reduces the probability of error correction. According to the present invention, it is possible to provide a similar error detection function not only to all other error correction codes based on multi-form logic, but also to other signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an error detection circuit to which the present invention is applied, FIG. 2 is a diagram showing packet I/correct reception-IIA after error correction by computer simulation, and FIG. is the first
Flowchart 1 for explaining the operation shown in the figure. FIG. 4 is a block diagram showing another actual flow side of the error detection circuit. 100... Output boat, 101... P/S, S/P conversion circuit, 102...
- Selector, 103...Data register, 104...Q adder modulo 2, 105...Input port, toe...Gate. 107...Adder modulo 2, 108...Timing generator, 108...Syndrome register, 110...Majority logic circuit, +11...Error detection circuit, +12...Clock signal, 113 ...Data before error correction, 114...Data after error correction, 1,,l 5...Reset signal, +16...Load signal, 117...Fetch signal, 88...Error status Signal, 119...Ready signal, 120...Data load control signal, 121...Data load pulse signal, +22...Data load clock signal, 123...So-called correction group I
・41 '1, 124... Error correction signal, 125... Syndrome shift clock signal, 126... Clock signal for fetch, 127... Serial load data, 128... Circulating data, 128...・Syndrome register signal, 130...
Threshold (ffi decrease signal, +31...Error correction impossible signal, 400...Encoder, 401...Counter. 402...Comparator, 403...OR circuit, 404...Par 11゛° Push button signal indicating, 405.
...Push button signal indicating °゛12°°, 406...
Push button signal indicating °°13°゛, 407...”1
4" push button signal indicating no limit, 408... reset signal, 410... error correction signal, 411-414... encoded signal of 404-407, 415. ...Output signal of counter 401, 416...
Error detection signal based on the number of error corrections, 417...Error detection signal from the syndrome register. Patent applicant Japan Broadcasting Corporation

Claims (1)

[Scope of Claims] l) In an error correction circuit for character code broadcasting using a majority set cyclic code error decoding system. The number of error correction bits generated by the syndrome register during cyclic correction is counted, and when the counted value reaches a certain value or more, even if the syndrome register is all zero, error detection is performed. An error detection circuit characterized by comprising a means for determining and reducing display of typographical errors. 2) The error detection circuit according to claim 1, characterized in that the specific A "1" is changed according to the state of the external receiver A. (hereinafter referred to as a margin)