JPS6091274A - Test system - Google Patents

Abstract

PURPOSE:To make a time from the setting of a parameter to triggering independently of an order practicing cycle, by reading the data of a parameter group from a practice table memory by address indication and setting the same to a register in one order cycle. CONSTITUTION:A superior processor 1 operated by a higher order language follows test content and sends the S-number thereof to an inferior processor 2 which is turn inputs the S-number to an index memory 6 and the leading address of a corresponding parameter block is obtained from a practice order table memory 5 in which the control order to a measuring module 7 is stored. In addition, the processor 2 repeats the interpretation practice of the parameter block and practices the test of LSI adaptor 8. Further, a parameter block system is brought to such a structure that a separate order or the same order is practiced in one order cycle.

Description

[Detailed Description of the Invention] [Field to which the invention pertains] The present invention relates to a test system, and more specifically, a test system for performing test 1 on a test object using a plurality of test modules having a predetermined test function. It relates to a test system configured in
Regarding the synchronization method, this invention relates to a control method that can determine the time from parameter set to trigger regardless of the instruction execution cycle.

[Prior Art] One type of test system is an analog t-SI test system. Generally, in such conventional systems,
Total of 7111 modules: When controlling the L-Rule, setting parameters for individual registers and generating trigger signals to synchronize circuit operations are executed by software using instructions from a different node.However, the purpose of synchronization is Although this has been fully achieved, since the instruction is divided into two, the limit for shortening the time from parameter set to trigger is the instruction execution cycle, and it is theoretically impossible to reduce the time below that. There was a drawback.

[¥f, Akira's Purpose] The purpose of the present invention is to eliminate such drawbacks and to provide a test system that can determine the time from parameter cell l- to 1-rigar J: independently of the instruction execution cycle. It's all about providing.

[Summary of the Invention] The processor can execute a program created by the upper processor (1 processor and lower processor 4), and the lower processor 11 can execute a program created by the higher processor (1 processor and lower processor 4). an execution table memory in which various parameter groups including a plurality of instruction codes are stored in advance in one parameter block, and a conversion for determining the start address of the various parameter groups corresponding to the specified number. Equipped with index memory where tables are stored, Processera! J-, J: Give the library specification number to the reindex memory and set the start address of the desired parameter group to 4f7. With this address specification, read the data of the parameter group from the execution table memory and set it in the register in one instruction cycle. It is characterized by being made possible.

[Example] The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the test system of the present invention.

In the figure, 1 is a high-level processor that can operate in a high-level language, and 2 is a low-level processor that can execute programs written in a high-level language. It's Tsusa. Upper and lower processors exchange data via a dedicated bus 4 and a bus buffer 3.

5 is an execution table memory in which various instructions for operating the measurement module 7 are stored, and 6 is an index memory having an index table for searching the start address of the various instruction programs stored in the execution table memory. It is.

7 is a pro to Tsuza 2 Jζsal! III+ is activated to execute a test of the LSI adapter 8 (analog LSI').

Note that the measurement module 7 is not limited to a fixed one, and can be exchanged and connected to various modules depending on the LSI adapter to be tested.

The operation in such a configuration will be explained next with reference to FIGS. 2 and 3. Individual contents (control commands) for controlling the connected measurement modules 7- are stored in the execution table memory 5, and each control command can be specified by its corresponding number (hereinafter referred to as S number). J: The sea urchin is turning. Top level [1 set! J-1GJ,, Tess]・
According to the contents, the S number is sent to the lower processor 2 via the bus 3 and bus buffer 3.

Manually inputting the S number to the processor 21J index memory 6 ←: SMf of the execution table memory 5
Obtain the starting address of the parameter group [1, ri] corresponding to the number.

Figure 2 shows an example of the basic structure of a parameter block. The first block 1o is an S number consisting of a 16-bit binary number, the next block 11 is the data length of the parameter block, and block 12 is the next block. Pointer P (
The pointer length PL indicates how many block 13) continues, the block 14 indicates what kind of pitch l-m structure the parameter body of the data (parameter string) 17 has, and the block 15 indicates the block 14. The name attached to the parameter itself (unique number @), block 16 is data 1
Control number (
C-NO> are written respectively. Parameters for such a configuration are set in an internal register (not shown) of the processor 2.

FIG. 3 shows an example of an r-statement for implementing such a register set.

In FIG. 3, SET represents a set command, M represents a word measurement module, and designation of r-rule, and PRMl represents a parameter identification name, and here the value of the identification name is Δ. This A
(parameter value) is the S number in FIG.

When the parameters are stored in the register of the processor 2 as described above, the processor 2 then repeats the interpretation and execution of this parameter block and executes the dest of the LSI adapter 8.

By the way, if the command ends with only the SET command as shown in Figure 3, there is no cutting margin problem, but when pasting multiple commands, the 4T parameter a[ ] tsuku format as shown in Figure 2 of IJ is used. When executed with the command, each stage 1 to 1-Ftj
In order to reach the S number, etc., it takes an extra time (cycle 1).

Therefore, we created a structure as shown in Figure 4 in the one-task format, and executed different instructions and the same instruction within one instruction code. The format shall be a parameter block suitable for The block structure in Figure 4 is the pointer (P) in Figure 2.
13 has been expanded into multiple parts. The statement in the case of such a block structure is as shown in FIG. Block 11
) to generate a trigger. Therefore, the instruction cycle is one cycle from the first CON instruction to the last SET instruction.

Note that the symbol "\," at the end of the eight instruction statements in FIG. 5 is a symbol indicating a range of instructions having the same timing from 1 to RIGA.

<I, the data arrays in Figures 2 and 4 are microb1]
By programming, high-speed processing can be achieved by simply changing the processor 2! It becomes possible to

Further, since the processor 2 is not limited at all, speeding up can be achieved by increasing the number of parallel processing pits.

[Effects of the Invention] As explained above, according to the present invention, the processor 1 and the processor 2 are distributed in the data arrangement as shown in FIG. It is possible to eliminate a lot of common access operations, and multiple parameter sets can be performed in one instruction cycle.
The speed of the entire system can be increased.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the main part 14 of an embodiment of the dest system of the present invention, Fig. 2 is a diagram showing the basic structure of the parameter block, and Fig. 3 is an example of an instruction statement. 1 and 4 are diagrams showing the structure of a parameter block employed in the present invention, and FIG. 5 is a diagram showing an example of a group of instructions processed in one instruction cycle. 160. Top professional tree, 2. ,, Lower Procera!
t, 3. ,,path buffer,/1. ,, private bus, 51
1. Execution table memory, 611. Index memory, 7. ,, Hf measurement module 88. . LSI adapter.

Claims (1)

[Claims] The parameters set in the register of
The I7 is connected to the measurement module that performs the specified test function, and is configured to perform a test on the object connected to this NI side module. +F4 is created to be able to execute the program created by It is equipped with an index memory in which a conversion table for storing the start address of the corresponding various parameter groups is stored, and the processor gives a designation number in nlj notation to the index memory by 1 to input the start address 1 of the desired parameter group. A test system is characterized in that data of a group of parameters from an execution table memory can be read out and set in a register in one instruction cycle by obtaining a node and specifying this address.