JPS6235699B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital circuit simulation device, and more particularly to a digital circuit simulation device that includes logic elements that operate in response to input data in parallel.

Recently, by integrating complex digital circuits using VLSI, performance relative to production costs has been relatively improved. When digital circuits are integrated using VLSI, it is possible to reduce the size and cost of the device, but this does not mean that there are drawbacks to VLSI. In other words, even if the degree of circuit integration is improved through VLSI, there is a limit to its ability to respond to technological changes, the time required from development design to manufacturing will be longer, and it will be difficult to detect and correct design errors. It's becoming very difficult. It is desirable to verify the design as early as possible in the development stage, as the existence of design errors will result in greater economic losses than before. Above all, it is important to thoroughly verify the logical functionality of the system at an early stage. This is because if a logical error is discovered at a late stage of design, a considerable amount of wasteful physical redesign is required.

For such circuit verification, there has conventionally been a circuit simulation method using a general-purpose computer. However, as the degree of integration increases as described above and the number of elements included in a system increases dramatically, there are limits to programming and execution processing using methods using general-purpose computers. That is, as the scale of the system to be verified increases, the amount of programs, storage capacity, and calculation time required for verification will increase significantly. This is because the operation of the target logic circuit is mainly parallel, and the input/output status of each part of the circuit changes at the same time, whereas general-purpose computers convert parallel operations into von Neumann-type sequential processing. This is due to the fact that it has to be expanded. In order to solve these problems, a hardware configuration using a parallel processing method or a pipeline method has been proposed, which makes it possible to shorten the execution processing time. However, until now little consideration has been given to improving programming.

Therefore, the main object of the present invention is to provide a digital circuit simulation device which can directly simulate logic elements operating in parallel in parallel, has a relatively simple configuration, and is inexpensive.

In summary, this invention allows data regarding each element included in a digital circuit to be stored for each element, and at the same time allows data of the next generation to be processed using historical data of a generation earlier than the generation in question. For history-dependent processing, data from a certain previous generation of interest is stored, and in response to input data being set from the input setting means of each element, or history data being set together with the input data, The configuration is such that a simulation is performed by executing calculations regarding the elements to which the data has been set.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a schematic block diagram of an input/output subsystem 1 included in FIG. 1, and FIG.
FIG. 2 is a schematic block diagram of the execution control unit 2 shown in the figure.

First, a general configuration of an embodiment of the present invention will be described with reference to FIGS. 1 to 3. A simulation device in one embodiment of the present invention is comprised of an input/output subsystem 1, an execution control unit 2, and a functional memory 3. The input/output subsystem 1, execution control unit 2, and functional memory 3 are connected by a common bus 4.

The input/output subsystem 1, as shown in FIG.
Input packet groups 11 to 13 corresponding to the number of inputs of the digital circuit to be simulated
, an arbiter 14 , output packet groups 15 to 17 corresponding to the number of outputs of the digital circuit, and a distributor 18 . The arbiter 14 selects a packet from one of the input packet groups 11 to 13 and supplies it to the common bus 4. In addition, the distributor 18 is connected to the common bus 4.
Output packets given by output packet group 1
This is for setting any one of 5 to 17.

As shown in FIG. 3, the execution control unit 2 is composed of a distributor 21 connected to a common bus 4, a plurality of templates 22 to 24, an arbiter 25, and an ALU 26. The distributor 21 is connected to the common bus 4 and is used to set data given from the input/output subsystem 1 or the functional memory 3 to any of the templates 22 to 24, or to send data calculated by the ALU 26 to the common bus 4. It is intended to be given to The templates 22 to 24, which will be explained in detail later in FIG. 4, store data regarding each element included in the digital circuit to be simulated. The arbiter 25 provides data read from one of the templates 22 to 24 to the ALU 26. ALU2
Reference numeral 6 has an arithmetic function that characterizes a basic element, ie, an AND gate in the case of an AND gate, and is used to calculate electrical characteristics peculiar to the element, such as transmission delay characteristics.

As will be explained in detail in FIG. 5 below, the functional memory 3 stores data in a state before the generation of interest, that is, a certain unit time before a clock pulse is input, such as in a D-type flip-flop, for example. It stores initial state data in a history-dependent element such that when the next clock pulse is input, the held data is used to determine its output state.

4 is a diagram showing data stored in the templates 22 to 24 shown in FIG. 3, FIG. 5 is a diagram showing data stored in the functional memory 3, and FIGS. 6A to 6C are diagrams showing data stored in the templates 22 to 24 shown in FIG. FIG. 7 is a diagram showing the contents of a transmitted packet, and FIG. 7 is a diagram showing an example of a digital circuit to be simulated according to an embodiment of the present invention.

As shown in FIG. 4, the template 22 is provided with an area for storing data regarding the NAND gate 8 shown in FIG. 7, for example. That is, this template 22 stores in advance data indicating that the NAND gate 8 is a two-input NAND, the amount of delay, the number of outputs, and data indicating that the output destination is one input terminal of the OR gate 10. . Also, data 1 and data 2 areas are provided as storage locations for input data. Similarly, the template 23 stores the same type of data regarding the OR gate 10, and the template 24 stores the same type of data regarding the D-type flip-flop 9. The template 24 stores data regarding the operation of the D-type flip-flop 9, and the data regarding the holding state of the D-type flip-flop 9 is stored in the functional memory 3 as described above.

That is, as shown in FIG. 5, the functional memory 3 is provided with areas 31 to 33 for storing data regarding an interface 30 and a plurality of flip-flops. In each area, data representing, for example, a D-type flip-flop is written as an element name, and the number of output connections of, for example, a D-type flip-flop is written in advance as an intra-generation reference circuit. Furthermore, each area is provided with a plurality of columns in which generation numbers, reference numbers, and data are stored as one set. Incidentally, since the digital circuit to be simulated shown in FIG. 7 is provided with only one D-type flip-flop,
In this example only area 31 is used. In the initial state, the generation number is set to 1 in the area 31, the number of references within the generation is set to 1 as the number of references, and the output state of the D-type flip-flop 9 in the initial state is set in the data field. 0 is written in all other terms.

Next, the specific operation of one embodiment of the present invention will be described with reference to FIGS. 1 to 7. Data corresponding to inputs 1-2 are provided to input/output subsystem 1. The input/output subsystem 1 creates packets IN1 and IN2 corresponding to inputs 1 and 2, and provides them from the arbiter 14 to the execution control unit 2 via the common bus 4.
When the execution control unit 2 receives the data of the packet IN1, the distributor 21 sets the data in the data 1 area of the template 22. Subsequently, the data of packet IN2 is similarly set in the data 2 area of template 22 and the data 1 area of template 24. In this way, template 2
When all the data necessary for arbiter 25 is set, template 22 becomes active, and the data set in template 22 is transferred to arbiter 25.
It is transferred to the ALU 26 via. ALU 26 performs the required operations based on the data set in template 22. That is, since the template 22 corresponds to the NAND gate 8, an AND operation is performed to calculate the logic and delay amount appearing in the output of the NAND gate 8. The result of this calculation is set in the data 1 area of the template 23 corresponding to the output destination set in the template 22, that is, the OR gate 10.

On the other hand, in the template 24, the data 1 area has been set, but the status area has not yet been set. The data to be set in this area is the initial state data of the D type flip-flop and is stored in the functional memory 3. In order to activate the template 24, it is necessary to read this data from the function memory 3, but this work is not necessary for the template 24.
It is triggered by the arrival of data 1 at . That is, the execution control unit 2
A read request packet 5 shown in FIG. A is given to the functional memory 3. This read request packet 5 includes information such as a D type flip-flop as the circuit element name, 1 as the generation number, and template 24 as the destination of the read data.
When the interface 30 included in the functional memory 3 receives the read request packet 5, it selects the area 3 corresponding to the circuit element name included in the read request packet.
Read data from 1. That is, from the area corresponding to generation number 1, the D type flip-flop 9
The data in the initial state is read, and the reference count is decreased by 1 to indicate that the data has been read once. The data read from the area 31 is configured by the interface 30 as a packet 6 as shown in FIG. 6B, and this packet 6 is sent to the execution control unit 2 via the common bus 4.
will be forwarded to. The execution control unit 2 determines that the data destination is the template 24 based on the packet 6 sent from the functional memory 3, and
Write read data to the status area of the template 24.

In this way, the template 24 becomes active with all data set, and each data is sent to the ALU 26 via the arbiter 25.
The data is transferred to , where the necessary calculations are performed. This calculation is for determining the operation of the D-type flip-flop 9, and is a calculation for determining the operation of the D type flip-flop 9.
The output state of the D-type flip-flop 9 is determined based on the data in the initial state given from the D-type flip-flop 9 and the data 1 corresponding to the D input. In this way, the calculated output data of the D type flip-flop 9 is the data 2 of the template 23.
area. Further, the execution control unit 2 performs processing for writing the calculated output data of the D type flip-flop 9 into the functional memory 3.

That is, the execution control unit 2 creates a write request packet 7 shown in FIG. 6C. This write request packet 7 includes a D type flip-flop as the circuit element name, 1 as the generation number, and the calculated D type in order to specify the area 31 of the functional memory 3.
The output data of type flip-flop 9 is included as write data. When the interface 30 of the functional memory 3 receives the write request packet 7, it searches for a column in which the number of references is 0 in the area 31 that matches the circuit element name included in the write request packet 7, and determines the generation of that column. A number that is 1 larger than the generation number of the input packet is written in the number field, the number of references within the generation is written in the reference number field, and write data is written in the data field.

On the other hand, the template 23 becomes active because the output data of the D-type flip-flop 9 is set in the data 2 area, and the necessary operation, that is, the template 23 corresponds to the OR gate 10, Performs a logical sum operation. The calculated data is then output from the distributor 21 to the packet OUT1 included in the input/output subsystem 1 via the common bus 4.

Subsequently, input data for the next unit time corresponding to the next clock pulse is given to the input/output subsystem 1, and the above-described operation is repeated to perform a simulation for each unit time. In this case, the output data of the D-type flip-flop 9 that operated in a certain generation is set in the data section of the area 31 of the functional memory 3, so that if the input 2 changes in the next generation, If the data is given, the output data of the D type flip-flop 9 is calculated by reading the data from the functional memory 3.

As mentioned above, an execution program can be created by setting data regarding each element included in the digital circuit to be simulated in a template for each element, and the relationship between the digital circuit to be simulated and the execution program can be created. It is possible to maintain consistency. The calculation order corresponding to each element is defined only by the data set in the template, and other order definitions can be made unnecessary. Furthermore, since the functional memory 3 is provided with individual areas for storing data related to history-dependent elements such as multiple flip-flops, even if multiple flip-flops are provided in the digital circuit to be simulated, each It becomes possible to access the functional memory 3 from the execution control unit 2 for the flip-flops.

Note that in a certain generation of processing, the functional memory 3
If there is no change in the write data set in , and the input of the next generation is the same as the input of the immediately previous generation, the D type flip-flop 9 will be activated in the next generation.
The output of does not change. Therefore, in such a case, if the input/output subsystem 1 outputs the data of the output packet of the previous generation as it is without forwarding the input packet, the generation that does not require calculation can be saved. can be skipped, improving processing efficiency. Furthermore, by providing a plurality of execution control units 2 and assigning each execution control unit 2 to each generation, each execution control unit 2 can equally share the calculations even in a complex digital circuit. can. the result,
Even if the digital circuit to be simulated includes many parallel processing parts, it can be processed at extremely high speed.

Furthermore, in the embodiment described above, the execution control unit 2 includes a plurality of templates 22 to 24.
Although the ALU 26 is provided, a plurality of ALUs 26 may be separated and provided as arithmetic units, and a plurality of execution control units 2 may also be provided. In this way, multiple parallel circuits can be processed simultaneously, making high-speed simulation possible.

As described above, according to the present invention, data regarding each element included in a digital circuit is stored, and for history-dependent elements, data of a generation earlier than the generation of interest is stored. In response to input data being set or history data being set together with input data for a history-dependent element, operations are performed on the element for which data has been set.
An executable program can be created that corresponds to the digital circuit to be simulated. The simulation execution order is determined depending on whether all data regarding each element has been set, and other order regulations can be made unnecessary. Therefore, simulation of a parallel digital circuit can be performed with a relatively simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of one embodiment of the present invention. FIG. 2 is a schematic block diagram of the input/output subsystem shown in FIG. FIG. 3 is a schematic block diagram of the execution control unit shown in FIG. 1. FIG. 4 is a diagram showing data stored in a template included in the execution control unit. FIG. 5 is a diagram showing data stored in the functional memory shown in FIG. 1. Figures 6A to 6C are diagrams showing packets. FIG. 7 is a diagram showing an example of a digital circuit to be simulated according to an embodiment of the present invention. In the figure, 1 is an input/output subsystem, 11 to 13 are input packets, 14 is an arbiter, and 15 is an input/output subsystem.
1 to 17 are output packets, 18 is a distributor, 2 is an execution control unit, 21 is a distributor, 22 to 24 are templates, 2
5 is the arbiter, 26 is the ALU, 3 is the functional memory,
8 is a NAND gate, 9 is a D-type flip-flop, and 10 is an OR gate.

Claims (1)

[Scope of Claims] 1. A digital circuit simulation device that simulates a digital circuit including a logic element and a history-dependent element in which data of the next generation is processed using data of a generation before execution of a certain process. Input setting means for setting input data to be input to each of the elements; history data storage means for storing history data of a generation before execution of the certain process of the history-dependent element; and information regarding each of the elements. a plurality of element data storage means for storing data for each logic element; and input data is set from the input setting means to any of the plurality of element data storage means, or the history data storage means is set together with the input data. Depending on the data set from
A digital circuit simulation device comprising execution control means for executing calculations regarding elements for which data has been set. 2. The execution control means includes means for setting data resulting from the execution of the calculation into an element data storage means corresponding to an element to which the output of the element is connected. The digital circuit simulation device according to item 1. 3. The execution control means includes means for storing result data obtained by execution of the calculation in the next generation of the history-dependent element in place of the data of the certain execution generation previous in the history data storage means. A digital circuit simulation device as claimed in claim 1.