JPS6091285A - Audio clock with multi-alarm function - Google Patents

Abstract

PURPOSE:To enhance convenience, by informing the next alarm setting time or non-setting by an audio signal after alarm informing operation. CONSTITUTION:The outputs of first, second and third alarm memories 24, 26, 28 are compared with the output of a preset counter 30 connected to a timing counter 14 corresponding to the signal of an alarm ON/OFF switch 20 by a comparator 22 and the output thereof is supplied to an audio informing start/stop circuit 34, a sound selecting circuit 48 and the next time alarm detecting circuit 52. In addition, alarm sound data, next alarm non-setting sound data and a next time alarm time code signal are respectively contained in first and second code ROMs 44, 46 changed over by a change-over circuit 28 and a time signal generating circuit 42 while the alarm informing signal and the next alarm time informing signal of the circuit 48 and the signal of the circuit 52 are imparted to the circuit 38 and a predetermined audio signal is generated from a sound emitting circuit 37. By this method, the presence and absence of the next time information are known.

Description

[Detailed Description of the Invention] The present invention relates to an improvement of a watch having a multi-alarm function that allows setting of multiple alarm times, and when multiple alarms are set, one alarm is notified. This invention relates to an audio watch with a multi-alarm function that later notifies the time of the next alarm by voice.

Conventionally, multi-alarm clocks have been configured so that each alarm can be set or not set for each alarm. Therefore, it is necessary to provide a means by which the user can determine whether each alarm is on or off and the time at which it is set. One example is
By switching and displaying the valley alarm time on one time display section and simultaneously displaying each alarm time and a set mark to indicate whether the alarm is sent or not, it is possible to distinguish between the alarm time and its sent status. There is something I did. Such a watch has the disadvantage that it is not possible to instantly know the alarm time and its cent status, and the operation is complicated.

- Another example is to provide a set mark in the corner of the display that indicates whether the alarm is set or not corresponding to each alarm, so that the set status of the alarm is always displayed, and the alarm time is displayed. Some models have a switching display in the section.

In such watches, it is possible to instantly determine which alarm is set, but the set time cannot be known without changing the display, and it is difficult to simplify the operation. there were. Further, in those using a liquid crystal display device, the number of segments for set marks must be increased, and there is a drawback that there are more restrictions on the arrangement of segment patterns, etc.

In the present invention, after one alarm notification operation, if another alarm is subsequently set, the alarm time is generated by voice, and if no other alarm is set, that effect is notified, and the next alarm is set. To provide a voice clock with a multi-alarm function that allows a user to recognize the setting state and time of an alarm without any operation.

An embodiment of the invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention. 1
0 is a reference signal generator consisting of a crystal oscillator, etc.; 12 is a frequency divider circuit that divides the frequency of the reference signal and outputs it as various frequency signals; and 14 is a frequency divider circuit that counts the time reference signal from the frequency divider circuit 12 and outputs a clock signal. 16 is a decoder driver that converts the clock signal into a display drive signal, and 18 is a display section including a liquid crystal display device or the like driven by the display drive signal.

Reference numeral 20 denotes an alarm on/off switch, which outputs signals A1, A2, and A3 for determining the on/off state of three alarms in this embodiment. 22 is a comparison circuit, which includes a first alarm memory 24 and a second alarm memory 26.
The stored value of the third alarm memory 28 and the output value of the preset counter 30 are compared, and when the alarm time stored in the memory corresponding to this signal is reached according to the states of the signals A1, A2, and A3, the signal B7, Either B8 or B9 and signal B11 are output. This preset counter 30
As soon as one alarm notification is completed, it is fast-forwarded by a high frequency signal to increase the count value in a short time.

At this time, the comparator circuit 22 compares the fast-forwarded contents of the preset counter 30 with the alarm time stored in the memory, and if they match, outputs a match signal. Thereafter, the preset counter 30 is reset and at the same time is set to the current time via the preset circuit 32.

Reference numeral 34 denotes a voice notification start/stop circuit, which is used to start and stop voice notification using a signal 81□ etc. from the ratio soft circuit 22.

36 is an audio signal emitting ηyu1111 j! 6, the operation is stopped by the signal G5 from the voice notification start/stop circuit 34, and the voice R is stopped from the address specified by the switching circuit 38.
The data in the OA 440 is read out and outputted as an audio signal, and the sound generation circuit 37 is driven to generate audio. Switching episode #! r38 includes the time signal generation circuit 4
2. 1st code ROM 44, 2nd code R, 0M46
These input signals are selectively outputted and applied to the audio monthly generation circuit 36. The signal G6 outputted from the time signal generation circuit 42 is "TSUGIHA".
It contains the code signals ``What Ji'' and ``What Hun'' and specifies the address for making the next alarm time audible. The signal output by the 0M44 includes the audio data of each alarm, for example, address designation data of "Ohayo", and is output via the switching circuit 38 when an alarm is notified.The second code ROM46
The output signal includes address designation data for the voice "Mounarimasen" indicating that the next alarm has not been set.

Reference numeral 48 denotes an audio selection circuit, which instructs alarm notification when its output signal CI rises, and instructs notification of the next alarm time when its output signal C2 rises. Output signal C
6 is a signal indicating that the notification operation has been completed, and is a signal for resetting the preset counter 30 and marking the preset circuit 32 via the delay circuit 50 to set the current time in the preset counter 30. be.

52 is a next alarm detection circuit, which generates a pulse in the output signal F6 to indicate this when the next alarm is not set, and does not generate a pulse in the output signal F6 when the next alarm is set. , thereby detecting whether or not the next alarm is set.

Alarm notification in this embodiment having the above configuration is as follows. First, when the alarm time comes, a predetermined alarm notification sound "Off you" is sounded.

If the next alarm is set at the end of this alarm's final operation, the time of that alarm will be set for one minute.
The system will make a voice announcement saying, ``Sanshuu Pun,'' and if the next alarm has not been set, it will make a voice announcement saying ``Mounari Maseno.''

FIG. 2 is a diagram showing the configuration of the alarm on/off switch 20 and comparison circuit 22 shown in FIG. 1.

54, 56, and 58 are switches for turning on and off the three alarms, and their respective output signals
2, A3 is applied to the comparison circuit 22.

The comparator circuit 22 includes memories 24, 26, 28 (Fig. 1).
AND circuits 60.62.64 which respectively input signals B1, B2, and B3 from the AND circuits 60.62.
64, and an OR circuit 68 which applies the signals from each AND circuit 60, 62, and 64 sequentially.
A match circuit 70 is provided which compares the signal from preset counter 30 (FIG. 1) with the signal from preset counter 30 (FIG. 1). The comparison circuit 22 also receives a match signal from the match circuit 70 and pulse signals B4, B5, B6 from the counter 66.
and No. 1g Al, A from the alarm on/off switch 20
2. AND gate 72.74.76 that inputs A3,
An AND gate 80 inputs the outputs of the AND gates 72, 74, and 76 via the OR gate 78, an output of the AND gate 80 is input to the clock input φ via the inverter 82, and the output Q is input to the AND gate 80. A flip-flop 84 is provided to apply the temperature.

The operation of the comparison circuit 22 will be explained separately for the case where the next alarm is set and the case where the next alarm is not set.

First, the case where the next alarm is set will be explained using the time chart shown in FIG. Incidentally, the times shown in the time charts after Figure 3 are tl, 11'
: Start of alarm notification, t2, [2': Alarm stops sounding, t3: Start of next alarm time notification, t4: Stop of next alarm time notification, 13': Start of "Mounari Masen" notification, 14': End of "Mounari Masen" notification , shows the passage of time.

As shown in FIG. 3, when switches 54 and 58 are turned on to send two alarms, the signal AI
, A3 are kept at 1-level and applied to the AND gate 72.76 of the comparison circuit 22.
, B6, and the matching circuit 70 are applied with matching signal power 1, respectively.

On the other hand, the AND circuits 60, 62, and 64 inputting the signals from the memory storing each alarm time sequentially input the signals from the memory at each timing of the signals B6, B5, and B4 output from the counter 66, respectively. It is applied to the matching circuit 70 via the OR circuit 68. Therefore, matching circuit 70
When it detects that the alarm time stored in the first alarm memory 24 has arrived, it outputs a coincidence signal at the timing of signal B4, and when it detects that the alarm time stored in the third alarm memory 28 has arrived, it outputs a signal B6. A match signal is output at the timing of . Therefore, when the coincidence signal outputted by the coincidence circuit 70 is output at the timing of the signal B4, a pulse of the signal B4 is generated only in the output signal B7 of the AND gate 72 which becomes open at the same timing. This signal B7 is generated at BAD via OR gate 78 and applied to AND gate 80. This AND gate 80 is normally open, and the signal HIO is
0 output signal B1□ is generated. At this time, signal B1
1 is inverted by the inverter 82 and applied to the clock power φ of the flip 70 knob 84. The flip-flop 84 switches the output state in synchronization with the rise of the signal BI2, and switches the output Q from the H level to the L level.
This closes the AND gate 80, and only the first pulse of the signal Blo is generated in its output signal B11. This signal B11 is applied to the audio notification start/stop circuit 34 to start the audio notification 11.

Thereafter, at time [2-1 ν, the switch 54 is turned off to stop the alarm from ringing, and the audio notification start/stop circuit 34, which will be described in detail later, outputs a signal DI11 and resets the flip-flop 84. The AND gate 80 is opened again. At the same time, the preset counter 30 (Fig. 1) is fast-forwarded, and the coincidence circuit 70 matches when the value of the precent circuit 30 reaches the next alarm time within a short time after the initial alarm notification has been stopped. Output a signal. In this example, the coincidence detection signal at this time is as follows, since the switch 58 is in the on state.
It is output at the timing of signal B6, and thereby a pulse is generated only in output signal B9 of AND gate 76.

The pulse generated in the signal B9 is generated in the signal B1□ via the OR gate 78 and the AND gate 80 located at the open Km. Due to the second pulse of this signal B11, notification of the next alarm time starts following the first alarm notification, and when this notification ends, it stops at time t4.

FIG. 4 is a diagram showing a time chart of the -j ratio circuit 22 shown in FIG. 2 when the next alarm is not installed. As shown in this figure, if the next alarm is not set, only the first alarm notification described above is performed. That is, a pulse is generated in the notification start signal Bll only once at time tl'.

Next, the configurations of the preset counter 30 and the precent circuit 32 which apply signals to the coincidence circuit 70 of the comparison circuit 22 shown in FIG. 2 will be explained using FIG. 5.

As shown in FIG. 5, the preset counter 30 includes a counter 86 that operates in synchronization with the time counter 14, and an OR gate 88 that applies a signal H2 to the counter 86.
An AND gate 90 applies a clock signal φ4 to this OR gate 88, and a high frequency (rm signal φ3) is applied to the OR gate 88.
It is composed of an AND gate 92 that applies , and an inverter 94 .

10,000, the grid reset circuit 32 is composed of a plurality of AND gates, and each of the AND gates has a
The outputs Q1 to Qo of the hour counter 14 are respectively applied,
Further, the output signal H of the delay circuit 50 is applied to the other input terminal.

Each output of the AND gate group of this precent circuit 32 is
The signals are applied to set inputs 81 to So of the counter 86 in the preset counter 30, respectively.

The operations of the preset counter 30 and the precent circuit 32 having such a configuration will be explained with reference to the time chart shown in FIG. Normal counter 86 is clock counter 1
It operates in synchronization with 4. That is, this counter 86 has
Clock signal φ4 is applied via AND gate 90 and OR gate 88, which are normally open, and continues counting at the same time as the current time. Therefore, when the count value of this counter 86 reaches the specified alarm time,
The coincidence circuit 70 (FIG. i2) in the comparison circuit 22 detects this and outputs a coincidence signal, and alarm notification begins.

Thereafter, the alarm is stopped sounding, and a signal F is output from the next alarm detection circuit 52 (FIG. 1), which will be described in detail later.
1 becomes H level, AND gate 92 becomes open instead of AND gate 90. Therefore, the high frequency signal φ3 is applied to the counter 86 via the at gate 92 and the OR gate 88, and the counter 86 is fast-forwarded. When the fast-forwarded count value of the counter 86 reaches the next alarm time, the matching circuit 70 (
(Fig. 2) detects this and outputs a coincidence signal again, and the notification of the next alarm time starts. After that, when the notification of the next alarm time is finished, the audio selection circuit 48, which will be described in detail later,
One pulse signal C6 is output from the counter 8.
6 is reset, and subsequently the AND gate group of the preset circuit 32 is opened. As a result, the counter 30 receives the clock counter 1 via the preset circuit 32.
The count value of 4 is applied as is, the current time is set, and the clock signal φ4 is input again to start counting.

Figure 7 shows the audio notification start/stop circuit 3 shown in Figure 1.
4 is a diagram showing the configuration of No. 4. FIG.

96.98.100 are signals B7, B8.15 . This is a clip-flop that inputs the clock signal φ to the clock input φ. This flip 70 tube 96.98
．． Output signals D3, D4, and D5 from each output Q of 100 are applied to one input terminal of an AND gate 102, 104, and 106, respectively. This and gate】02.10
4,106, the signals AI, A2, A3 from the alarm on/off switch 2° are connected to the inverter 1o8.
．． A one-shot multivibrator 114 that outputs a pulse based on the rising edge of the signal inverted at 110 and 112.
, ■16.118 output signals D□D15,])16 are applied. Such an and gate■02.10
4.106 output signals 1) 17, ■) 18, DI9 are:
The output signal D20 of the OR gate 120 is generated.

Reference numeral 122 denotes a clip-flop which inputs the signal B1□ from the comparison circuit 22 and the code 3 from the next alarm detection circuit 52 to the cent power S via the OR gate 124.

From the output Q of this clip-flop 122, a signal J)
2 is output, and in response to this signal D2, a signal G5 is output from the AND gate 126 to which the signal φ2 is input. Also,
A signal D2□ is output from the output Q of the 7-linopflop 122, and is sent to the flip-flop 96.98.1 via the OR gate 128 together with the signal C2 from the audio selection circuit 48.
It is applied to the reset input R of 00.

On the other hand, the output of the OR gate 130 is applied to the reset manual power ratio of the flip-flop 122. This OR game 1-130 inputs the output signal of the OR gate 120 and the output signal of the OR gate 132, and this OR game 1-132 further inputs the outputs of the AND gates 134 and 136. The AND gate 134 inputs a signal G2 from a time signal generation circuit 42 and a signal C2 from an audio selection circuit 48, which will be described in detail later, via a one-shot multivibrator 138.
is the signal C2, the audio signal, the signal G from the signal generation circuit 36, and the next alarm detection circuit 52 via the inverter 140.
It inputs signal F5 from .

The operation of the audio notification start/stop circuit 34 having such a configuration will be explained using the time charts shown in FIGS. 8 and 9.

FIG. 8 shows a time chart when the switches 54 and 58 shown in FIG. 2 are turned on and the next alarm is set. When the first alarm time is reached, a pulse is generated in the output signals B7 and B1□ of the comparator circuit 22, as described above. When a pulse is generated in the signal B7, the flip-flop 96 sets the output Q to the H level in synchronization with the rising edge of the pulse, thereby opening the AND gate 102.

On the other hand, when a pulse occurs in signal B11, OR gate 1
The flip-flop 22 is sent through the gate 24, the signal D2 rises to H level, and the signal φ2 is generated as the output signal G5 of the AND gate 126. This output signal G5 is transmitted to an audio signal generation circuit 36, which will be described in detail later.
is applied to the address counter and serves as a drive signal for the address counter when reading data from the audio ROM 40. Therefore, when the signal G5 is output, the audio signal generation circuit 36 is activated and alarm notification starts.

Thereafter, the switch 54 shown in FIG. 2 is turned off, and the signal Al1J'! When the signal falls to the -L level and an instruction is given to stop the alarm, the one-shot multi-pipe leak 114 or pulse is output by the rise of the signal inverted by the inverter 108. This pulse passes through AND gate 102, which is already open, and further passes through ORGATE 120 to generate signal D20.

The flip-flop 122 is reset by the pulse generated on the signal 1]2o, which closes the AND gate 126 and stops the address counter in the audio signal generation circuit 36.
will also be reset.

Further, this signal D20 is applied to the next alarm detection circuit 52 (FIG. 1), which will be described in detail later, and is applied to the signals 1 and 1 for fast forwarding the preset counter 30 described above.
is output. When the preset counter 30 is fast-forwarded and the comparison circuit 22 detects the next alarm time,
As described above, a pulse is generated in the signal Bll again. This causes the AND gate 12 to return as described above.
The signal φ2 is generated in the output signal G5 of No. 6, the audio signal generating circuit 36 is activated, and notification of the next alarm time is started.

When the next alarm time is read out from each memory circuit, etc. as "Tsugiha wa ji wa huun", the signal G2 output from the time signal generation circuit 42, which will be described in detail later, becomes L level as shown in FIG. This signal G2 becomes H at the end of
At the same time as the level rises, a pulse is output from the one-shot multivibrator 138. At this time,
Since the signal C2 output from the audio selection circuit 48 is set to reach the I level at the same time as the second pulse of the signal Bll is generated, the anti-game) 134 is in an open state, and from the one-shot multi-byte break 138. The output pulse is passed through an AND gate 134 and an OR gate 132,
130 to flip-flop 122.

. Then, the 7-ring 70-segment 122 is reset, and the AND gate 126 is thereby closed again, and the notification of the next alarm time is also terminated. FIG. 9 shows a time chart when the next alarm is not set.

The operation is the same as that described above until the alarm is first sounded and then stopped.

When the next alarm is set, signal B1 is activated again.
1, but the next alarm is not set as described above, the comparator circuit 22 outputs the signal 1.
311 is not pulsed again. However, instead of this, the next alarm detection circuit 52 detects that the next alarm has not been sent and generates a pulse on signal F3. The pulse generated at this signal +yI++3 sets the flip-flop 122, opens the AND gate 126, and causes the audio signal generation circuit 36 to
is made.

The voice announced at this time is "Mounarimasen."

When "1 MOUNARIMASEN" is read out in this way, a pulse is generated in the output signal G1 of the audio signal generation circuit 36, and the flip-flop is output via the AND gate 136 and the OR gate 132 and 130, which are kept open by the impark 140. 122.

When the 7-lip flop 122 is reset in this manner, the notification of ``1-1 MOUNARIMASEN'' indicating that the next alarm has not been set ends. FIG. 10 is a diagram showing the configuration of the audio signal generation circuit 36 shown in FIG. 1.

The audio signal generation circuit 36 includes a start address designation ROMI 42 that designates the first address when reading data from the audio storage U M 40, an end address designation ROM 1 44 that designates the last address, and an address designation/reader ROM 146. , a matching circuit 148 that detects that the last address has been read, a DA converter 150 that converts data from the audio ROM 40 into an analog signal, and a low-pass filter 152 that cants high frequency components.
It is composed of an AND gate 154 for providing an interval between the audio signal "Ohayo" and the next "Ohayo".

The operation of the audio signal generating circuit 36 having such a configuration will be explained next.

FIG. 1J and FIG. 12 are diagrams showing the timing of the audio signal generation circuit 36 when the next alarm is set and when it is not sent.

This audio signal generation circuit 36 is instructed to read data from the audio ROM 40 by the output signal G3 of the switching circuit 38, and is stopped in operation by the output signal G5 of the audio notification start/stop circuit 34 described above.

When alarm notification is instructed by signal q3, a signal designating the first address of alarm notification audio data in audio 140M40 is applied from start address designation ROM 14.2 to address counter 1461. At this time,
When signal G5 is applied to address counter 146, address counter 146 starts!・Address specification ROM
The data in the audio ROM 40 is read from the address specified by 142.

The data read from this audio ROM 4.0 is i
) -A converter 150 converts the signal into an analog signal, passes through a low-pass filter 152 and applies it to an analog signal ( ) 154 , and then to an amplifier 156 in the sound generation circuit 37 . This amplifier 156 then drives the speaker 158 to generate the sound "Ohayo".

10,000, the end address designation ROM 144 is instructed by the signal G3 to indicate the last address of the data to be read from the audio ROM 40, and transmits that address to the matching circuit 148. This matching circuit 148 counts 11 of the address counter 146.
and the value specified by the end address designating ROM 144, and when they match, a pulse is generated in the signal G.

When a pulse is generated on GH, the address counter 146 again starts reading data from the audio ROM 40 from the address specified by the start address designation ROM 142.

Thereafter, when the switch is operated to instruct to stop the ringing and a pulse is generated in the output signal DIO of the OR gate 130 shown in FIG. 7, the signal G5 applied to the address counter 146 is fixed at L level, The counter 146 stops and the alarm notification ends. At this time, if the next alarm is set, the signal G will be activated again.
5, the address counter 146 starts counting and the notification of the next alarm time starts. At this time, the signal G3 has already changed to a signal for notifying the next alarm time, and indicates the address for notifying the next alarm time to the start address designation ROM 142 and the end address designation ROM 144. Therefore, address counter 1
46 reads out the next alarm notification audio signal from the audio ROM 40, and reads the next alarm notification audio signal from the sound generation circuit 37 as described above.
Generates "Nokino Shichiji Sanjuupun".

If next alarm 1 is not set, after the alarm notification has stopped sounding, signal G3 indicates that the next alarm has not been set.
This causes the voice R to be output as shown in FIG. 12.
From the OM 40, only data for voice notification of "Mounari Masen" is read out.

In this way, the audio signal generating circuit 36 is instructed by the signal G3 from the switching circuit 38 which data to read from the audio ROM 40.

Next, this switching circuit 38, the time signal generation circuit 42, the first
The relationship between the code ROM 44 and the second code ROM 46 will be explained using FIGS. 13 to 16.

FIG. 13 is a diagram showing the configuration of the time signal generation circuit 42. This time signal generation circuit 42 has 1 "nogiha", "ji"
, "Nokiha" code ILOM 160 that stores each code signal for the sound "Hun", "Ji" code R (
The JM 162 is composed of a J code ROM 1 64, a multiplexer 166 that inputs signals from these ROMs and time-related signals from the preset counter 30, and a heptad counter 168 that determines the output state of the multiplexer 166. ing.

This time signal generation circuit 42, as shown in FIG.
When the audio notification is performed, the heptadium counter 168 is reset by the signal D1 output from the audio notification start/stop circuit 34 described above, so that the output signal G6 is
The state of the will be changed in various ways. That is, heptad count 16
8 is reset, its output Q1 becomes H level.

As a result, the signal from the "Tugino" code ROM 160 is generated as the output signal G6 of the multiplexer 166. This signal G6 is applied to the above-mentioned audio signal generation circuit 36 via the switching circuit 38, and the sound generation circuit 37 produces the sound "Tsugino."

At this time, the audio signal generation circuit 36 generates a pulse signal G indicating that the sound "Nogiha" has been read out from the audio box 0M40. This signal Gl is the clock input φ of the time signal generation circuit 4207 base counter 168.
This pulse advances the count by one, and the output Q2 becomes 1. -Become I level. Output Q
2 becomes H level, a code signal related to the hour digit of the next alarm time is generated in the output signal G6 of the multiplexer 166, and the voice "shichi" is similarly generated. After that, a pulse is generated for each word in the signal G1, which advances the count value of the hexadecimal counter 168, and the output signal G6 of the multiplexer 166 is a voice code signal necessary for sequentially notifying the alarm time. occurs, and when the output Q7 of the hexadecimal counter 168 becomes H level, a signal G2 indicating the end of alarm time notification is output.

10,000, the first code I also has a voice code related to "Ohayo" which is an alarm notification voice in 0M44, and the next alarm is not written in the second code 0M46. A voice code related to the voice "mounarimasen" is stored.

These time signal generation circuit 42, first code ROM 44,
The switching circuit 38, which inputs the signal from the second code R (JM46), switches and outputs the signal from the time I= signal generating circuit 42, etc., depending on the state of the input signals C□ and C2F5. That is, as shown in FIG. As shown, when the signal C] becomes 1-level, the first code ROM 44 outputs the IR signal to notify the alarm, and when the signal C2 also becomes H level, the signal from the time signal generation circuit 42 is output. The next alarm time will be announced.

Further, as shown in Fig. 16, when the signal C1 becomes I- (level) and the signal F5 becomes H level, the signal from the second code R, 0M46 is output and the next alarm is not set. inform about something.

Next, the audio selection circuit 48 that applies the signals C1 and C2 to the switching circuit 38 and the next alarm detection circuit 52 that applies the signal F5 will be explained in order.

FIG. 17 is a diagram showing the configuration of the audio selection circuit 48. 1
As mentioned above, 70 is a control flop that inputs the output signal Bll of the comparison circuit 22, which generates a pulse at the time of alarm notification and next alarm time notification, to the clock input φ, and 172 inputs the signal B1□ to the clock input φ. Input,
It is also a flip-flop that inputs the output Q of the flip 70 tube 170 to its D input. This flip flop 17
The output signal of 0 is the signal c1, and the flip-flop 17
The output signal of No. 2 is signal c2. The signal C2 is also applied to one input of the AND gate 174, and the other input of this AT gate 174 is connected to the aforementioned time signal generation circuit 42.
A signal G2 indicating the end of the next alarm time notification is applied. Output signal C4 of this AND gate 174
is the OR gate 1 together with the signal F6 which is output when the next alarm detection circuit 52 does not output 4 capsules of the next alarm.
The output of the OR gate 176 is applied to the reset input R of the flip-flop 170, 172, and at the same time to the one-shot multivibrator 178.

FIG. 18 is a time chart of the audio selection circuit 48 when the next alarm is set, and FIG. 19 is a time chart when the next alarm is not set.

When alarm notification is first started, a pulse is generated in the signal B1□. This pulse causes the flip flow knob 1
The output Q of 70 rises to the high level, and the signal C1 becomes high.
level...and instructs the switching circuit 38 described above to issue an alarm. After that, if the next alarm is set, a pulse is generated again in the signal B1□ as described above.

In this way, when a re-pulse occurs on signal 3□1,
Since the signal Cl is already at j-level, the output Q of the flip-flop 172 becomes H level. This causes signal C2 to go to HL/bell, turning off M Ir1
It instructs the l path 38 to notify the next alarm time. When the next alarm time notification ends, the signal G2 output from the time signal generation circuit 42 rises from the L level to 1-1 novel, and thereby the output of the AND gate 174 becomes H level. This signal C4 resets the flip-flops 170 and 172 via the OR gate 176 to return them to their initial states, causing the one-shot multivibrator 178 to output a pulse. This pulse signal C6 is used to reset the fast forwarded preset counter 3o as described above, open the gate of the preset circuit 32, and set the current time in the preset counter 3o.

On the other hand, if the next alarm is not set, no pulse will be generated in the signal BII again after the alarm notification ends, so the output of the 7-lip-frog 172 will be kept at the L level. Thereafter, a pulse that is output when the next alarm detection circuit 52 does not detect the next alarm is generated in the signal F6, thereby returning the Noritub flops 170 and 172 to their initial states. The next alarm detection circuit 52 will be explained using the diagram.

Reference numeral 180 is a 12-hour or 24-hour counter, which is operated by a clock signal φ3 applied through an AND gate 182. This at-gate 182 is opened and closed by the output Q of the flip-flop 184. The flip 70 knob 184 sets the output Q to H level in synchronization with the rise of the signal D20 output from the audio notification start/stop circuit 34 when the alarm is stopped sounding, and outputs the signal from the counter 180 applied via the OR gate 186. of (f
It is reset by the i number F3 or the signal B1□ from the comparator circuit 22. The output signal F3 of the counter 180 is also applied to the clock input φ of the flip 70 knob 188, and the flip-flop J8.8 sets its output Q to H level in synchronization with the rise of the signal F3. It is. This flip-flop 188 outputs a signal F5, and this signal B'5 is applied to an AND gate 190 which receives the signal (3,) output from the audio signal generating circuit 36 described above.

The operation of the next alarm detection circuit 52 having such a configuration will be explained using the time charts shown in FIGS. 21 and 22.

First, alarm notification is started, and when it stops sounding, a signal D20 indicating that the alarm notification has ended is emitted.
A pulse is generated. Due to the pulse of this signal D2o,
Flip-flop 84 changes its output state to bring output Q to H level. When the output Q of this flip-flop 184 reaches level 14, the analog gate 182 becomes open, the clock signal φ3 is applied to the counter 180, and the counter 180 starts counting. This counter 180 performs a callantra Q operation at the same time as the counter 86 in the brisset counter 30 described above is fast-forwarded.

Here, if the next alarm is set, a pulse is generated in the signal B1□, as shown in FIG. signal BI
When a pulse is generated on I, flip-flop 184 is reset, its output Q goes to L level, and AND gate 182 becomes open. At the same time, 7 ring 7a
The output Q of the plug 184 becomes H level, and the counter 180 is thereby reset. That is, counter 180
If the comparison circuit 22 detects the next alarm time before the counter 180 counts up, the counter 180 is stopped counting without counting up. When the output signal F3 of the counter 180 remains at the L level in this manner, it indicates that the next alarm is being sent. On the other hand, if the next alarm has not been sent, no pulse will be generated in @No. 13-1 even if the alarm notification ends. Therefore, the clip-flop 184 causes the counter J, 80 to count up and generate a pulse on the signal F3! It will never be reset. Therefore, the counter 180 counts up and generates a pulse in the output signal II'3. This pulse generated at F3 is to notify that the next alarm is not set and is applied to the audio notification start/stop circuit 34. When a pulse is generated, the output Q of the Norinob flop 188 rises to the H level.In this way, when the signal F5 reaches the I (level), the audio notification start/stop circuit is activated to notify that the next alarm has not been set. 34 and the switching circuit 38. At this time, the AND gate 190 is opened, and the signal G1 indicating that data reading has been completed is passed and generated as the signal F6. This indicates that no alarm has been set, that is, that the notification of "Mounarimaseno" has ended.

As described above, according to this embodiment, the alarm is first announced by the voice "Ohayo", and at the weak point where the next alarm is set, the set time of the next alarm is announced by the voice [Nokihashichijisanjunopun]. ” will be announced. Furthermore, when the next alarm has not been set, the alarm notification is followed by a voice notification "Mounarimasen". In addition, in the above embodiment, there are three alarm functions,
The explanation was given using an example where one or two of them are set, but the operation is the same even if all of them are set, and the earlier set time will be notified as the next alarm time. do not have.

The effects of the present invention are shown below.

(1) It is possible to instantly determine whether or not the alarm will sound next time.

(2) Since there is no need to display whether or not an alarm is set on the display section, the display section does not need to be complicated.

(3) The next alarm time can be known without any operation.

(4) Since the notification is made by voice, it is possible to Q without understanding the content of the notification without looking at the display.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the configuration of the comparison circuit shown in Fig. 1, and Fig. 3 is a diagram showing the configuration of the comparison circuit shown in Fig. 2 when the next alarm is set. The time chart of the comparison circuit, Figure 4 is the time chart of the comparison circuit shown in Figure 2 when the next alarm is not set, 4
Figure 5 shows the configuration of the preset circuit and preset counter shown in Figure 1, Figure 6 is a time chart of the preset counter shown in Figure 5, and Figure 7 shows the configuration of the audio notification start/stop circuit shown in Figure i1. Fig. 8 is a time chart of the audio notification start/stop circuit shown in Fig. 7 when the next alarm is set, and Fig. 9 is a time chart of the audio notification start/stop circuit shown in Fig. 7 when the next alarm is not set. A time chart of the notification start/stop circuit, FIG. 10 is a diagram showing the configuration of the audio signal generation circuit shown in FIG.
Figure 1 is a time chart of the audio signal generation circuit shown in Figure 10 when the next alarm is set, and Figure 12 is the time chart shown in Figure 10 when the next alarm is not set.
A time chart of the P signal generation circuit, FIG. 13 is a diagram showing the configuration of the time signal generation circuit shown in FIG. 1, and FIG. 14 is a diagram showing the configuration of the time signal generation circuit shown in FIG.
Time chart of the time signal generation circuit shown in Fig. 3, No. 15
The figure shows the time chart of the switching circuit shown in Fig. 13 when the next alarm is set, Fig. 16 shows the timing chart of the switching circuit shown in Fig. 13 when the next alarm is not set, and Fig. 17 shows the timing chart of the switching circuit shown in Fig. 13 when the next alarm is not set. Figure 1 shows the configuration of the audio selection circuit, Figure 18 is a time chart of the audio selection circuit shown in Figure 17 when the next alarm is set, and Figure 19 is when the next alarm is not set. 17 is a time chart of the audio selection circuit, FIG. 20 is a diagram showing the configuration of the next alarm detection circuit shown in FIG. 1,
Gu? Figure 2J shows the second alarm when the next alarm is set.
Quimchar of the next generation alarm detection circuit shown in Figure 0), i
Figure 22 shows the 20th alarm when the next alarm is not set.
3 is a time chart of the next alarm detection circuit shown in the figure. 10... Reference signal generator, 12... Frequency divider circuit, 14...
...Clock counter, J6...Tecoder driver, 1
8... Display unit, 20... Alarm on/off switch, 22... Comparison circuit, 24... First alarm memory, 26... Second alarm memory 28... Third alarm memory, 30...・・Preset counter, 32・
...Preset circuit, 34...Audio notification start/stop circuit, 36...Audio signal generation circuit, 38...Switching circuit, 37...Sound generation circuit, 4o...Audio ROM
, 42... Time signal generation circuit, 44... First code ROM, 46... Second code ROM, 48... Audio selection circuit, 52... Next alarm detection circuit. Patent Applicant: Rhythm Watch Industry Co., Ltd. Figure 21 Time-to-f Go-3 Figure 22 Japanese J--Bun 11111stop11''■

Claims (1)

[Claims] A clock circuit that counts a constant periodic signal for a time measurement reference using a time counter and displays the count value of the counter;
A plurality of alarm time memories each storing a predetermined alarm time, an alarm on/off switch that enables or disables the alarm time signal from each alarm time memory, and an alarm time signal and a clock counter from the alarm time memories. In a watch with a multi-alarm function, the watch has a comparison circuit that compares the time signal from the clock and outputs a matching signal if they match, and a sound generation circuit that generates an alarm notification sound when the matching signal is output. ,
a preset counter that counts the current time in conjunction with the time counter, and compares the current time with a plurality of alarm time memories in the comparison circuit instead of the time counter; data and
An audio ROM in which second audio data indicating that the next alarm notification is not set is stored, and an audio signal for generating a desired audio in the sound generation circuit is created based on the audio data from the audio ROM. an audio signal generation circuit;
a time signal generation circuit that specifies first audio data in the audio ROr'A based on the count value of the preset counter and causes the audio signal generation circuit to read out the first audio data;
A code ROM that specifies second audio data in tOM and reads it out to the audio signal generation circuit, and a count value of a preset counter and other alarm time memories when the alarm on/off switch is operated and alarm notification is stopped. Press the fast forward pulse until the
and a next alarm detection circuit which outputs a mismatch signal if they do not match, and operates the audio signal generation circuit based on the match signal from the comparison circuit and the mismatch signal from the next alarm detection circuit. an audio notification start/stop circuit that stops the operation by operating the alarm on/off switch; and an audio selection that outputs a selection signal that selects the audio to be generated based on the match signal from the comparison circuit and the mismatch signal from the next alarm detection circuit. circuit and the selection signal of the audio selection circuit, the code R
a switching circuit that selects data from either the OM or the time signal generation circuit and supplies it to the audio signal generation circuit; a preset circuit that presets the count value of the time counter to the preset counter after the audio notification ends;
A voice clock with a multi-alarm function characterized by: