JPS6093509A - Input and output module of programmable controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to handshaking (data transfer) between an input/output module of a programmable controller (hereinafter referred to as PC), specifically, a PC and the input/output module. The present invention relates to an input/output module that can exchange data without requiring confirmation means (between sending and receiving data).

[Background technology]

Figure 1 shows a conceptual diagram of the PC system. In conventional input/output modules, in the case of numerical input/output data, data was exchanged by handshaking with the PC for each data unit, but while the data was being exchanged, the PC was on standby. Since the system is in a temporary state, when the amount of numerical input/output data is large, the processing efficiency of the PC often decreases.

Therefore, a RAM is provided between the input/output module and the PC to temporarily hold the input/output data, and when outputting data from the PC to the input/output module, the data is written to the RAM, and the PC receives the data from the input/output module. When inputting data, it is conceivable to read the data from the RAM to facilitate data transfer.

As an earlier application disclosing such technology, Japanese Patent Application Laid-Open No. 1986-
9804 and JP-A-57-62414.

However, the former method uses a serial signal between the receiving and transmitting sections, and cannot be applied to a method where data is exchanged using parallel signals.

Furthermore, in the latter case, the hole AM is built into the FC side, and a means for specifying the input/output module is required. Furthermore, since the PC does not directly drive the input/output module but indirectly drives it, there is a drawback that the processing speed cannot be improved unless a copy of the RAM is stored in another memory.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and aims to improve the processing efficiency of a PC by enabling data exchange without handshaking, and to provide an input/output module that can be used as standard. The purpose is to provide.

[Summary of the invention]

The gist of the present invention is to intelligently configure the module by equipping the input/output module with a nimoji processor, and also to provide a dual port AM and give access priority to the RAM to the PC. Furthermore, when the RAM access of the FC is completed, an access completion signal is generated and the access right is handed over to the module processor, thereby synchronizing with the scanning of the PC.

[Embodiments of the invention]

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an input/output module according to the present invention, and has the configuration described below.

Reference numeral 1 denotes a module processor, which controls the entire input/output module.

2 is a ROM in which instructions to be executed by the module processor 1 are stored.

3 is the RA of the working area of module processor 1
It is M.

4 is an external interface that converts input signals from external equipment into a format (level) that can be used by the input/output module, and vice versa.

5 is a random access memory, which temporarily holds input/output data. Furthermore, after this, Il
o It is called RAM.

6 is an access controller for Ilo RAM5;
All access signals for Ilo RAM 5 are generated by this.

A bus controller 7 controls whether or not signals from a data bus 8 and an address bus 9 connected to the PC are input to the input/output module.

Reference numerals 10a and 10b are data transmitters, which receive signals from the access controller 6 and the bus controller 7 and regulate the direction in which data flows.

Gates 11a and llb receive signals issued by the access controller 6 and bus controller 7, respectively, and transmit or disconnect address signals.

The above Ilo RAM 5, access controller 6,
bus controller 7, data transmitter 10a,
10b, Gates lla and llb, Pu'er boat A
It constitutes M.

In the figure, extremely obvious signal lines (for example, a control signal line to be sent from the module processor 1 to the ROM 2) are omitted.

〔motion〕

Next, a more detailed explanation will be given according to specific operations.

When the PC imports data from the input/output module,
The city is designated by control signal 12.

The control signal 12 specifically includes a module designation signal, an output designation signal, and the like.

The module designation signal designates a specific input/output module, since generally a plurality of input/output modules are connected to one PC.

The output designation signal designates whether data is to be read or written. In this case, it is a read.

This control signal 12 is received by the controller 7.
issues a signal 13 requesting the access controller 6 to access IloRAM.

In response, the access controller 6 returns a response signal 14 if it is accessible, and also sends a read signal 15 to the I10 AM 5 to enable reading.

The bus controller 7 sends a signal 17 to open the gate 11b, inputs an address signal from the PC, and sends a signal 18 to open a path for data to flow from the Ilo RAM 5 to the PC.

Through the above operations, the contents of the Ilo RAM 5 are read out by the PC.

Furthermore, when the PC outputs data to the input/output module, it designates this using the control signal 12, as in the case of reading/inputting. When data writing is specified, the bus controller 7 issues an Ilo RAM access request signal 13 to the access controller 6. The access controller 6 returns a response signal 14 if access is possible. If the module Brocenosa occupies Ilo AM and cannot be accessed, the response signal 14
won't return. This is necessary to prevent the PC from accessing the Ilo RAM when the module processor initializes the Ilo RAM during initial reset. The PC normally accesses the input/output module, and not only does it not access the Ilo AM but also does not participate in the state of the input/output module.

Upon receiving the response signal 14, the bus controller 7 transmits the signal 1.
7, the address signal from the PC is transferred from the gate 1113 to the Ilo AM address bus, and the signal 18
is given to the transmitter 10b, and the data from the PC is sent to the transmitter 10b.
lo Ordinarily put on the AM data bus.

Furthermore, the access controller 6 is Ilo ll AM5
A write signal 16 is sent to the host to collect data.

Through the above operations, the PC data is written to the Ilo AM5.

When the access to the Ilo RAM 5 by the PC is completed, the module designation signal in the control signal 12 is cut off, and the bus controller 7 outputs the completion signal 1.
Emit 9. In response to this completion signal 19, the module processor 1 issues a signal 20 to the access controller 6 to start accessing the Ilo RAM 5.
The data in RAM 3 in the working area is read out and transferred to the RAM 3 in the working area, and the data in RAM 3 in the working area is transferred to
Transfer (write) to lloltA. Note that the data transmitter 10a and the gate 11a are
= Controlled according to reading and writing by signals from the controller 6.

Module processor 1 performs this access as follows:
This is the period from the end of PC access to the start of access in the next PC scan.

In other words, even if the module processor 1 attempts to access the Ilo AM 5 at any other time, the P
Since C is accessing, the signals 21 and 21' branched from the signal 18 or 18' that regulate the data transmission route between the PC and the I10RAM are input to the access controller 6, and these signals and the module processor 1 When the signals 20 from the WA I T signal 22 are input simultaneously,
This is because the command is issued and the access operation of the module processor 1 is temporarily stopped.

In other words, the PC is configured to give priority to accessing the Ilo RAM 5.

By doing this, the handshaking that was previously required, that is, the input/output module becomes
It is now possible to send and receive data without returning the U,SY double signal (a signal that causes the CPU to wait so that input/output commands are not executed), and I,' ORAM access can now be synchronized with PC scans.

〔Effect of the invention〕

As described above, according to the present invention, data can be exchanged between the PC and the input/output module without handshaking, and the processing efficiency of the PC can be improved. Moreover, since the data is not converted into a special format, it can be used as a standard.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a PC system, and FIG. 2 is a specific embodiment of the present invention. 1: Module Brocenosa 5: Ilo 11LA
M Figure 1 Procedure amendment 1. Display of the case 1988 Patent Application No. 201838 2, Title of Invention Programmable Controller Input/Output Module 3,
Relationship with the case of the person making the amendment Patent applicant address 2346-5 Fujita, Yahatanishi-ku, Kitakyushu, Fukuoka Prefecture
, Number of inventions increased by the amendment 0 6. Column 7 of "Detailed description of the invention" of the specification subject to the amendment, content of the amendment (1) Specification inner cylinder 3 @ 18iir handshaking"
ET Masashi Shimazu on "Handshaking". (2) Change “Signal 18” to “Signal 18-” on page 8, line 19 of the specification.
” will be corrected. (3) From line 7 to line 15 on page 8 of the specification, it is stated that ``The module processor uses IloRAM...
・We are not involved in the situation. ” will be deleted. (4) After page 10, line 19 of the specification, it says: [When the PC accesses the input/output module while the module processor is initializing IloRAM, the input/output module is initial reset 1.
A response signal 14 is not returned in response to the I10RAM access request signal 13, and access to the I10RAM by the PC is prohibited. In this case, the input/output module) to the PC is in the same state as if it were not installed. Therefore, no inconvenience occurs in the input/output processing of the PC. When the initialization of l10RΔM is completed, data is exchanged between the PC and the input/output module according to the procedure described above. ” will be inserted. that's all

Claims (1)

[Claims] The input/output module of the programmable controller is equipped with a module processor and a dual port RAM, and data is exchanged between the input/output module and the programmable controller by writing to and reading from the RAM. - When the controller attempts to access the RAM, the module processor also accesses the RAM.
When attempting to access M, the module processor is temporarily stopped and the programmable controller completes the access to the RAM.