JPS6097724A - Contact signal input circuit - Google Patents
Contact signal input circuitInfo
- Publication number
- JPS6097724A JPS6097724A JP58206727A JP20672783A JPS6097724A JP S6097724 A JPS6097724 A JP S6097724A JP 58206727 A JP58206727 A JP 58206727A JP 20672783 A JP20672783 A JP 20672783A JP S6097724 A JPS6097724 A JP S6097724A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- current
- contact
- power supply
- primary winding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Programmable Controllers (AREA)
Abstract
Description
【発明の詳細な説明】
く産業上の利用分野〉
本発明は、シークンス制御装置等へ接点信号を入力づる
場合の入力回路に関する。更に詳しく述べれば、5VD
C等の低電圧電源を用いて各人ツノ端へ接点信号をセン
スする為のセンス電流を供給し、前記接点信号のAン・
オフ状態に関連し/jセンス電圧信号を015VDC等
充分な大きさで後続のデジタル論理回路へ伝達すること
が出来る接点信号入力回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input circuit for inputting contact signals to a sequence control device or the like. To explain in more detail, 5VD
A sense current for sensing the contact signal is supplied to each horn end using a low voltage power supply such as C, and the contact signal A/
The present invention relates to a contact signal input circuit that is capable of transmitting a /j sense voltage signal of sufficient magnitude, such as 015 VDC, to a subsequent digital logic circuit in relation to an off state.
〈従来技術〉
第1図は従来の接点信号入力回路の餞型例を示4回路図
である。本図において、1.2は入力端子で、これら端
子に接点3inが接続される一方、線路W + 、 W
2が接続されている。線路WIは、センス電流を供給
する為の電流制限抵抗R0を介し、本回路の後段に接続
される論理回路をPH勢づる電源と同じ、例えば5vの
低電圧電源E1が接続されている。線路W2はコモンラ
インとなっている。R+ 、C+は接点Si nにクリ
ーニング電流を供給する為の時定数回路を構成する抵抗
並びにコンデンサ−Cある。線路W1中に段εノられた
ダイオードD1は、接113inが外部の池の負荷を合
わけて操作しているどき電流が回路に流れ込まないよう
にLJる為の電流逆流防止用ダイA−ドである。B2は
、クイA−ドD+の順方向電圧を相殺づる為に線路1−
1に挿入された補償用ダイオードである。R2は受信抵
抗、C2は接点入ツノ信号のヂャタリング成分を平滑づ
る為のコンデンサ、B1は受信抵抗R2の両端電圧を増
幅して後続の論理回路にノjえるバッファ増幅器で、5
vの低電圧電源「2か電源とし゛〔加えられている。<Prior Art> FIG. 1 is a four-circuit diagram showing an example of a conventional contact signal input circuit. In this figure, 1.2 are input terminals, and 3-inch contacts are connected to these terminals, while lines W + , W
2 are connected. The line WI is connected to a low voltage power source E1 of, for example, 5V, which is the same as the power source that powers the logic circuit connected to the subsequent stage of this circuit, through a current limiting resistor R0 for supplying a sense current. The line W2 is a common line. R+ and C+ are a resistor and a capacitor C which constitute a time constant circuit for supplying a cleaning current to the contact S in. The diode D1 inserted in the line W1 is a current backflow prevention diode A to prevent the current from flowing into the circuit when the connection 113in is operating the load of an external pond. It is. B2 is connected to line 1- in order to cancel the forward voltage of quad A-D+.
This is a compensation diode inserted at 1. R2 is a receiving resistor, C2 is a capacitor for smoothing the jitter component of the contact input horn signal, and B1 is a buffer amplifier that amplifies the voltage across the receiving resistor R2 and outputs it to the subsequent logic circuit.
V low voltage power supply "2" is added as a power supply.
回路定数を第1図中に記入したように定めIこ場合、接
点3inのAン・Δ)動作に対して第2図に示づような
動作をする。第2図に於いて図(a)は接J気3inの
動作状態を、 図(b)はコンデンサC1の両端電圧e
clを、 図(C)は接点SinのAン・Aノ動作に応
じて流れる電流11の状態を、図(d)はバッファ増幅
器B1の人ノj電圧e C2の状態を夫々示1波形図で
ある。In this case, the circuit constants are determined as shown in FIG. 1, and the operation is as shown in FIG. 2 for the 3-inch contact A.DELTA.) operation. In Figure 2, figure (a) shows the operating state of the 3-inch J air connection, and figure (b) shows the voltage e across the capacitor C1.
cl, Figure (C) shows the state of the current 11 flowing in response to the A/A operation of the contact Sin, and Figure (d) shows the state of the voltage e and C2 of the buffer amplifier B1.1 Waveform diagram It is.
バッフ?増幅器13盲を例えばC−MO8論理素子で構
成したとき、ルベル(「1は入力端子が5V、Oレベル
値は入力電圧がO■となるようにJれば理想的であるが
、実際には接点信号入力回路はルベルが下降傾向を持ち
、0レベルが上脣Jる傾向を持つ。これは接点3inの
導線抵抗がOレベルを上昇させ、接点3inの絶縁低下
がルベルを下降さぼるからである。Buff? For example, when the amplifier 13 blind is configured with C-MO8 logic elements, it would be ideal if the input terminal is 5V for 1 and the input voltage is O for the O level value, but in reality In the contact signal input circuit, the level tends to fall, and the 0 level tends to rise.This is because the resistance of the 3-inch contact wire increases the O level, and the drop in insulation at the 3-inch contact causes the level to fall. .
〈従来技術の欠点〉
第1図に示J従来回路の場合、 第2図(d)で示すよ
うにルベル値は4V10レベル値は0.75 Vとなり
、ルベル並びに0レベルのスレシホールド・マージンを
低下させる欠点があった。<Disadvantages of the prior art> In the case of the J conventional circuit shown in Figure 1, the Lebel value is 4V, and the level value is 0.75V, as shown in Figure 2(d), and the threshold margin of the Lebel and 0 levels is It had the disadvantage of lowering the
単純に、ルベルの電圧を上昇さゼる為に、電源E、を5
■から6vに上げただけでは、ルベルのスレシホールド
・マージンの向上は計れるが、Oレベルの電圧は0,7
5 Vから1.4vに上って、Oレベルのスレッシホー
ルド・マージンは低下してしまう。Simply turn the power supply E to 5 to increase the voltage of the level.
If you just raise it from ■ to 6V, you can improve the Lebel threshold margin, but the O level voltage is 0.7V.
As the voltage increases from 5 V to 1.4 V, the O level threshold margin decreases.
電源E1を電源[2より高く選び、ダイオードDoをイ
4加する方法も考えられるが、電源に別種の電源が必要
どなり、それだ【ノー1ストが嵩むことになる。It is possible to choose the power source E1 higher than the power source [2 and add a diode Do, but this would require a different type of power source, and that would increase the no.
〈目的〉
本発明の[1的は、木図WBの後段に接続される論理回
路をjllシリる電源と同じイ1(電圧電源を用いなが
ら、変化幅の人さなセンス電圧を出力出来る接点信号入
力回路を実現することにある。<Purpose> The first object of the present invention is to provide a contact that can output a sense voltage with a small variation range while using a voltage power supply, which is the same as the power supply that connects the logic circuit connected to the subsequent stage of the tree diagram WB. The purpose is to realize a signal input circuit.
〈発明の構成〉
本発明の構成は、1次巻線、2次巻線を有りる相互イン
ダクタンス手段と、前記1次巻線を第1の極性で電源へ
接続して電流を注入づる第1のスイッチと、na記記法
次巻線第2の極11で電源へ接続して電流を放出さける
第2のスイッチと、前記2次巻線の入力端子に接続され
た接点と、前記1次巻線に接続された受信抵抗とを段【
〕、前記電源にこの回路の後段に接続された論理回路を
附勢する電源と同じlit電圧電源を用い、前記1次巻
線の電流放出期間に前記接点信号をセンスする為のセン
ス電流を前記2次巻線側に流し、前記接点の状態に応じ
た前記2次巻線の両端電圧を前記1次巻線に伝達し、前
記受信抵抗より前記接点信号のセンス電圧を発生させる
ようにしたものである。<Configuration of the Invention> The configuration of the present invention includes a mutual inductance means having a primary winding and a secondary winding, and a first inductor which connects the primary winding to a power source with a first polarity and injects current. a second switch connected to the power supply at the second pole 11 of the secondary winding, a contact connected to the input terminal of the secondary winding; The receiving resistor connected to the line and the stage [
], the same lit voltage power supply as the power supply that energizes the logic circuit connected to the latter stage of this circuit is used as the power supply, and the sense current for sensing the contact signal is supplied to the above during the current discharge period of the primary winding. The voltage is applied to the secondary winding side, and the voltage across the secondary winding according to the state of the contact is transmitted to the primary winding, and the receiving resistor generates a sense voltage of the contact signal. It is.
〈実施例〉 第3図は本発明の実施例を示J回路図である。<Example> FIG. 3 is a circuit diagram showing an embodiment of the present invention.
本図において、第2図におりる要素と実質的に同じ要素
には同一符号をイリし説明は省略づる。11は1次膠線
し+ 、2次巻線L2より構成された相nインダクタン
ス手段どし−Cの変成器で、1次、2次の巻線比1:1
の単純なセパレーション・タイプのものが用いられる。In this figure, elements that are substantially the same as those in FIG. 2 are designated by the same reference numerals, and their explanations are omitted. 11 is a transformer with phase n inductance means and -C, which is composed of a primary winding + and a secondary winding L2, and the winding ratio of the primary and secondary windings is 1:1.
A simple separation type is used.
電源E1と電流制限抵抗R9に接続されたスイッチ3
W 101、 並びにコモンと1次巻線L+の一端にダ
イオードD3を介し接続されたスイッチS W 102
とは、1次巻線11に第1の極性で電流を注入する為の
第1のスイッチを構成する。尚、ダイオードD3は1次
巻線り、への電流の方向を限定するために挿入されてい
る。Switch 3 connected to power source E1 and current limiting resistor R9
W 101, and a switch S W 102 connected to the common and one end of the primary winding L+ via a diode D3.
constitutes a first switch for injecting current into the primary winding 11 with a first polarity. Note that the diode D3 is inserted to limit the direction of current flowing to the primary winding.
コモンと、 スイッチS W 101と電流制限抵抗R
oとの接続点に接続されたスイッチ5W201、並びに
5vの低電圧電源E3と、 スイツy−8W102どク
イA ド1つ3どの接続点との間に接続されたスイッチ
5W202は1次逆線し!に第2の極性で電源を接続し
て電流を放出させる為の第2のスイッチを構成覆る。common, switch SW 101 and current limiting resistor R
The switch 5W201 connected to the connection point with O, and the switch 5W202 connected between the 5V low voltage power supply E3 and the connection point with the switch 5W202 are primary reverse wires. ! A second switch is configured to connect the power supply with a second polarity to the second polarity and discharge current.
Oム記第1のスイッチど第2のスインJ−とを相?il
i的に繰り返し操作Mるとぎ、前記第1のスイッチを介
して1次巻線(−1に電流が注入され、前記第2のスイ
ッチを介し、1次巻線L1から電源へ電流が還元される
。この還元電流は2次巻線L2にも分流し、コンデンサ
C+を充電づるが、この」ンデン勺の両端電圧が1次巻
Pit L、 +の電源電圧に達づると、2次巻線L2
へのエネルギー注入は起らなくなり、1次巻線L1のみ
を通って還元電流が流れる。Is the first switch of the Omu in phase with the second switch? il
After repeated operations M, current is injected into the primary winding (-1) through the first switch, and current is returned from the primary winding L1 to the power source through the second switch. This reduced current is also shunted to the secondary winding L2 and charges the capacitor C+, but when the voltage across this capacitor reaches the power supply voltage of the primary winding L2, the secondary winding L2
No energy injection occurs and the reduction current flows only through the primary winding L1.
接点3inがΔ)状態で1つ、電流還元時には、5■の
電源E3がダイオードD、ll!Iを介して接続される
為、クイオードD3のアノード側には、5■の電源電圧
より高い電圧が発生する。このときのビークrUi圧の
充電によってコンデンサC2の電圧eC2は5■に保持
される。When the contact 3in is in the Δ) state, one, and when the current is returned, the 5■ power supply E3 is the diode D, ll! Since it is connected through I, a voltage higher than the power supply voltage of 5■ is generated on the anode side of the diode D3. By charging the peak rUi pressure at this time, the voltage eC2 of the capacitor C2 is maintained at 5.
−n %接点3 i nがAン状態で且つ、電流還元時
には、変成器[+02次側のインピーダンスが低く、電
流は2次巻線L2のみを流れる。 この電流によって2
次巻線に発生した電圧は1次巻線[1に複写され、この
電圧がダイオードD211!!を介した値となって与え
られ、コンデンサC2にはビD電圧が伝達される。-n % Contact 3 i n is in the A state and at the time of current return, the impedance of the transformer [+0 secondary side is low, and the current flows only through the secondary winding L2. This current causes 2
The voltage developed in the secondary winding is copied to the primary winding [1, and this voltage is transferred to the diode D211! ! The VD voltage is transmitted to the capacitor C2.
第4図は複数の接点信号入力回路を一式のスイッチで附
勢する場合の実施例を承り回路図である。FIG. 4 is a circuit diagram of an embodiment in which a plurality of contact signal input circuits are energized by a set of switches.
本図において、第1図及び第3図にJハブる要素と実質
的に同じ要素には同一符号がイー1されている。In this figure, elements that are substantially the same as those in FIGS. 1 and 3 are designated by the same reference numerals.
5W101 ’ 、 5W102 ’ は第1のスイッ
チを構成づる1−ランジスタで、夫々のベースにバッフ
ァ増幅器B2 、B3を介し例えば250K l−I
Zのスイッチング信号が加えられている。5W201
’ 、 5W202′ は第2のスイッチを構成づるダ
イオードである。5W101' and 5W102' are 1-transistors constituting the first switch. For example, 250K l-I
A Z switching signal is added. 5W201
', 5W202' are diodes constituting the second switch.
図中に記入したように定数を定めた場合、第5図の波形
図で示すような動作をする。第5図に於い−C図(a)
は接点3inの動作状態を、図(b)は1次巻Ell
1.、 +を流れる電流1[+の状態を、図(C)は2
次谷線L2を流れる電流IL2の状態を、図(d)は前
記第1スイツヂの状態を承り波形図である。When the constants are determined as shown in the figure, the operation is as shown in the waveform diagram of FIG. 5. In Figure 5 - Figure C (a)
Figure (b) shows the operating status of the 3 inch contact, and Figure (b) shows the operating status of the 3 inch contact.
1. , Figure (C) shows the state of current 1 [+ flowing through +, 2
Figure (d) is a waveform diagram showing the state of the current IL2 flowing through the second valley line L2, depending on the state of the first switch.
接点3 i nがAフのとさ、ffR流の還元は、1す
]間Taで起こり、 電流制限抵抗Roとクイオード5
W201’ どの接続点には、 」モンがらダイA−l
’5W201 ’ ノJ:oツ7分0.5vを差引イタ
、−O,!iVの電ハ゛c 「” 、が発生し、グイA
−ド]〕2のアノード側に1.L、1−5■の電源E3
に2個のダイオード3W202 ’ 、D3によるドロ
ップ分を加えた電圧e「2が発生し、ダイオード5W2
02’とダイオードD3との接続点には、rri源E3
にダイオード5W201’ のダイオード・ドロップ分
を加えた+5.5Vの電圧ef、が光′U!Jる。コン
デン”j’ C2は、このときのピーク電圧にJzっC
充電され、この二Jンi′ンυの両端電圧ec2は5V
に保持される。When contact 3 in is in Af, the reduction of ffR current occurs between Ta and current limiting resistor Ro and quasiode 5.
W201' At which connection point is the "mongara die A-l"
'5W201' ノJ: Subtract 0.5v for 7 minutes Ita, -O,! iV's electric shock "" occurs, and
1 on the anode side of 2. L, 1-5■ power supply E3
A voltage e'2 is generated by adding the drop caused by the two diodes 3W202' and D3, and the diode 5W202'
At the connection point between 02' and diode D3, there is an rri source E3.
+5.5V voltage ef, which is the sum of the diode drop of diode 5W201', is the light 'U! Jru. Capacitor "j' C2 is JzzC at the peak voltage at this time.
When charged, the voltage ec2 across the two terminals is 5V.
is maintained.
一ノj接点Si nがAンのどさ、還元電流は2次1!
する。 このとき、 2次巻IIL−2の両端には、0
.75 V (タイ;t t’D+ (7)Fロyフ分
0,5Vk:、100J−ムの抵抗R+を平均電流2.
5mAが流れたことによって生じたドロップ分を加えた
電圧)が発生し、 これが1次巻線に複写される。 こ
ノ0,75 Vハブ T:ンカラ’j イA−ト5W2
01 ’ 。The first J contact Si n is A, and the reduction current is 1!
do. At this time, there are 0 at both ends of the secondary volume IIL-2.
.. 75 V (Tie; t t'D+ (7) 0.5 Vk:, 100 J-m of resistance R+ with an average current of 2.
A voltage (plus the drop caused by the 5mA flowing) is generated, and this is copied to the primary winding. Kono 0,75 V hub T: Nkara'j IA-to 5W2
01'.
D2の2個のダイオード・ドロップ分を介した値となっ
てコンデンサC2に伝達される為、コンデン4J−02
には1口電圧が伝達される。Since the value is transmitted to the capacitor C2 via the two diode drops of D2, the capacitor 4J-02
A single port voltage is transmitted to the terminal.
〈効果〉
本発明によれば、相互インダクタンス手段を有効に利用
することによって、後続の論理回路を附勢Jる電源と同
じ低電圧電源を用い、電源電圧以−Lの電圧を発生する
ことが出来、ルベル、Oレベル何れの場合も充分なスレ
シホールド・マージンのあるセンス電IEが得られる。<Effects> According to the present invention, by effectively utilizing the mutual inductance means, it is possible to generate a voltage lower than the power supply voltage using the same low voltage power supply that energizes the subsequent logic circuit. A sense voltage IE with a sufficient threshold margin can be obtained for any of the output, level, and O levels.
更に、回路中に前記相互インダクタンス手段による絶縁
要素が付加された為、装置内外のコモン電位差の影響を
受番ノることがなく、且つ高耐L」−がFurthermore, since the insulating element by the mutual inductance means is added to the circuit, it is not affected by the common potential difference inside and outside the device, and has a high resistance L.
第1図は従来の接自信号入力回路の曲型例を示1回路図
、第2図は第1図に承り従来回路の動作を説明する為の
波形図、第3図は本発明の実施例を示す回路図、第4図
は本発明の他の実施例を示J回路図、第5図は第4図に
示す本発明の実施例回路の動作を説明−4る為に波形図
でである。
11・・・相互インダクタンス手段、1−1・・・1次
巻線、1−2・・・2次巻線、5W101 、5W10
2 、5W101 ’ 、 5W102 ’ ・・・第
1のスイッチを購成するスイッチ、 5W201 、5
W202 、5W201 ’ 。
5W202’ ・・・第2のスイッチを構成するスイッ
チ、3 i n =・・接点、 R2・・・受信抵抗、
E+ 、R2。
R3・・・同種の低電F1電源。Fig. 1 is a circuit diagram showing an example of the curved shape of a conventional contact signal input circuit, Fig. 2 is a waveform diagram for explaining the operation of the conventional circuit based on Fig. 1, and Fig. 3 is a circuit diagram showing an example of the shape of a conventional contact signal input circuit. A circuit diagram showing an example, FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a waveform diagram to explain the operation of the embodiment circuit of the present invention shown in FIG. It is. 11... Mutual inductance means, 1-1... Primary winding, 1-2... Secondary winding, 5W101, 5W10
2, 5W101', 5W102'...Switch for purchasing the first switch, 5W201, 5
W202, 5W201'. 5W202'...Switch constituting the second switch, 3 in =...Contact, R2...Receiving resistor,
E+, R2. R3...Similar low-voltage F1 power supply.
Claims (1)
段と、前記1次巻線を第1の極性で電源へ接続して電流
を注入覆る第1のスイッチと、前記1次巻線を第2の極
性で電源へ接続して電流を放出さゼる第2のスイッチと
、前記2次巻線の入力端子に接続された接点と、nts
記1次巻線に接続された、前記接点の状態をレンス乃る
受信抵抗とを有し、前記電源としてこの回路の後段に接
続される論理回路を附勢りる電源と同じ低電圧電源を用
い、前記1次巻線の電IJfj放出期間に前記接点信号
をセンスづる為のセンス電流を前6[!2次巻線側に流
し、前記接点の状態に応じた前記2次巻線の両端電圧を
前記1次巻線に伝達し、前記受信抵抗より前記接点信号
のセンス電l工を発生させるJ:うにした接点信号入力
回路。a first switch for connecting the primary winding to a power supply with a first polarity to inject current; a second switch for connecting the winding to the power supply with a second polarity and discharging current; a contact connected to the input terminal of the secondary winding;
It has a receiving resistor connected to the primary winding that senses the state of the contact, and uses the same low voltage power source as the power source that energizes the logic circuit connected at the later stage of this circuit as the power source. 6 [! to the secondary winding side, transmitting the voltage across the secondary winding according to the state of the contact to the primary winding, and generating a sense electrician of the contact signal from the receiving resistor. contact signal input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58206727A JPS6097724A (en) | 1983-11-02 | 1983-11-02 | Contact signal input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58206727A JPS6097724A (en) | 1983-11-02 | 1983-11-02 | Contact signal input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6097724A true JPS6097724A (en) | 1985-05-31 |
Family
ID=16528102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58206727A Pending JPS6097724A (en) | 1983-11-02 | 1983-11-02 | Contact signal input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097724A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6335325U (en) * | 1986-08-26 | 1988-03-07 |
-
1983
- 1983-11-02 JP JP58206727A patent/JPS6097724A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6335325U (en) * | 1986-08-26 | 1988-03-07 |
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