JPS609873Y2 - Data processing device with one-chip direct memory access controller - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data processing device equipped with a one-chip direct memory access control device, and in particular, a one-chip direct memory access control device that manages direct memory access control in which a channel directly accesses memory. A data processing device that includes a chip direct memory access control device, reduces the number of external pins used on the chip, and allows a plurality of input/output ports forming the channels to have a common configuration. It is.

In general, in microcomputers, the CPU chip is rarely used alone, but rather in combination with peripheral chips.

For this reason, a CPU chip, a memory chip, a plurality of input/output port chips, etc. are usually connected to the data bus line.

In the above system, the channel performs so-called direct memory access control (hereinafter abbreviated as DMA control for simplicity) in which the channel directly accesses the memory.
In the present invention, since each output port chip has the same configuration, a DMA controller chip is commonly provided in each input/output port section, and the DMA control is managed by the DMA controller.

However, in this case, the DMA control device grasps the DMA request signals from the plurality of input/output ports, and also sends and receives DMA operation permission signals etc. based on the request signals.
Doing so increases the number of external pins used on the DMA controller chip.

This invention aims to solve the above points,
An m-ary counter is prepared on the DMA control device chip, and depending on the contents of the counter, DM from each input/output port section is controlled.
The purpose of this invention is to provide means for selectively taking in the A request signal, thereby reducing the number of pins used.

Therefore, a data processing device equipped with the one-chip direct memory access control device of the present invention has at least a central processing unit section and a plurality of one-chip input/output port sections having the same configuration as the memory, on the data bus line. is connected,
In the data processing device in which the input/output port section can directly access the memory, a one-chip direct memory access control device for managing the direct memory access control is provided, and the control device includes an m-adic counter and an operation mode of the counter. It has a word count register for instructing the counter, and a direct memory access instruction storage section for controlling the increment of the counter, and further includes a word count register for instructing the m-adic counter, and a direct memory access instruction storage section for controlling the increment of the counter. a selection means for scanning the direct memory access control requests of the above, and the selection means selects the direct memory access control request signals from each of the input/output port sections to cause the control device to generate the request; While executing the direct memory access control service according to the request, the device sets the instruction storage unit to stop the increment of the m-ary counter, and further, depending on the state of the operation instruction bit of the word count register, performs the above instruction storage section. After returning a response signal and completing the actual direct memory access operation, either restart the increment of the m-adic counter (interlace mode), or continue to stop and perform direct memory access of the input/output port section. The feature is that the control is exclusive (burst mode).

This will be explained below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the data processing device of the present invention, and
The figure shows an embodiment conceptually showing the structure of a direct memory access control device, and FIG. 3 shows an explanatory diagram illustrating the bit structure of the word count register WCR shown in FIG. 2.

In Figure 1, 1 is a central processing unit (CPU chip)
, 2 is a memory (memory chip), 3 to 10 are respective input/output port units (input/output port chips), 11 is a direct memory access controller (DMA controller chip),
12 is a bus switching circuit, 13 is a data bus line, 14 is a memory bus line, and 15 is a multiplexer that converts the DMA request signal from each input/output port into the contents of the subchannel counter (see Figure 2), 1 A decoder 16 decodes 1c0 and 1c1 of the subchannel counters and distributes the DMA operation permission signal to the corresponding input/output port section.

Each of the input/output ports 3 to 10 is connected to an input/output device (not shown), and controls data transfer between the input/output device and the memory 2.

Each input/output port has the same configuration, for example, to transfer data in units of 8 bits, #0 input/output port 3 constitutes the #O channel, and #1 output port 4 constitutes the #1 channel. , #2 output port 5 constitutes #2 channel, #additional and #J input/output ports 7 together constitute #3 channel with a data width of 16 bits, and #44 output port part 8 constitutes #4 channel, #5
u and #i input/output ports 9 and 10 are together 16
It constitutes #5 channel with a data width of bits.

Specifically, channels #0 to #3 are allowed to directly access the memory 2 under the control of the DMA control device 11.

Note that the bus switching circuit 12 connects the upper byte line U and lower byte line 1 of the data bus line 13 and the memory bus line 14.
It has a function of switching the correspondence between the upper byte line U and the lower byte line.

As conceptually shown in FIG. 2, the DMA control device 11 includes a memory address register (MAR) 17, a word count register (WCR) 18, and a subchannel register.
A counter (SC) 19 and a DMA control circuit 20 are provided.

The memory address register 17 is a register that stores address information for the memory during DMA control.
For example, it is made up of 16 bits and can specify up to 65 addresses.
1 of the memory 2 via the data bus line 13 shown in FIG.
A word (2 bytes) can be specified.

The word count register 18 corresponds to the direct memory access instruction storage unit according to the present invention, and is provided in each channel GHQ to CH3 in a one-to-one ratio, and is used to specify the number of words or bytes to be transferred during DMA control.
For example, it consists of 16 bits, the upper 4 bits are used for control commands such as specifying word/byte transfer, and the remaining 12 bits specify the number of words or bytes.

That is, of the illustrated mode specifying section of the word count register 18, the G-1/941 section specifies the transfer direction to the memory 2 during DMA control.

The subchannel counter operation instruction unit is for managing the progress of the subchannel counter 19 shown in the figure, and is for channel CHO.
If the contents of the operation instruction section in each word count register 18 corresponding to CH3 to CH3 are all logical 0, the illustrated channel counter 19 continues to increment.

When the contents of the operation instruction section of the word count register 18 corresponding to any one channel, for example, the channel CH1, are at logic rIJ, the contents of the subchannel counter 19 stop incrementing at a state of 101J. It's made to look like you're doing it.

The word/byte section specifies whether to transfer words or bytes. Since there are channels that perform word transfers, such as channel CH3 in Figure 1, and channels that perform byte transfers, such as channel opening or channel 2, it is necessary to specify conduct.

The ADR15 section inputs the illustrated memory address during byte transfer.
It specifies either the upper byte or the lower byte of one word specified by the contents of register 17, and is added to the bottom of memory address register 17 when DMA control is performed by byte transfer. The signal is transmitted to the memory 2 and the bus switching circuit 12 shown in FIG. 1 via signal lines.

The content of the bit ADRl 5 is incremented by 1 every time one byte is transferred, and it goes without saying that when a carry occurs, the carry amount is added to the least significant bit of the memory address register 17. .

A total of 12 bits in the word/byte number designation section designate the number of words during word transfer or the number of bytes during byte transfer, and can specify up to a maximum of station words or bobytes at one time.

Each time a 17-word or 1-byte transfer is performed, the contents of the number designation section are incremented by one, and when the contents become all zeros, it indicates that the transfer under the DMA control has ended.

In the illustrated case, the subchannel counter 19 indicates that the channel managed by the DMA control device 11 is GHQ or CH.
3, the counter 19 is composed of a binary counter, and the counter 19 runs on its own and reads the bits scg and sc.
1 is '00. , '01 J.

'10yo, '11yo, 'ooJ...' and so on.

For example, when 100 yo is indicated, the contents are supplied to the multiplexer 15 and the decoder 16.

In multiplexer 15, if DMA request signal DRQQ from channel GHQ is on, the request signal is supplied to DMA control device 11, and the contents of subchannel counter 19 are stopped at 100J.

When the DMA operation permission signal DOP is supplied to the decoder 16, the decoder 16 selects channel GHQ,
It is supplied to channel GHQ as the permission signal DOPQ.

As a result, channel GHQ enters DMA service under the control of DMA control device 11.

When the DMA service of that channel GHQ is completed, the contents of the subchannel counter operation instruction section of the word count register WCRQ of channel GHQ are all set to logic r''.
If OJ is set, subchannel counter 1
The content of 9 is 101yo.

r″10J, '11J'00J, etc., and the step is resumed (increment mode).

Of course, while the contents of the subchannel counter 19 are updated and channels GHQ to CH3 are being scanned, if any one channel DMA request signal is generated, the request is sent to the multiplexer 15 according to the contents of the counter 19. The signal is supplied to the DMA control device 11 via.

On the other hand, if there is a subchannel in which one or more of the four contents of the subchannel counter operation instruction section is set to logical rIJ, the counter is fixed to the subchannel of logical rIJ that the subchannel counter reaches first, The subchannel is exclusively used for DMA service (burst mode).

To cancel the burst mode, all contents of the subchannel counter operation instruction section must be set to logic 10.

As described above (DMA control device 11 has multiple channels GHQ)
When entrusting control to CH3 or CH3, generally DMA
The control device 11 provides at least DRQ for each channel.
A signal pin and a DOP signal pin are required.

On the other hand, in the case of the present invention, the m-adic channel
In order to take out the contents of the counter to the outside, there are log2m pins and common pins for DRQ signal and DOP for each channel.
All you need to do is add a signal pin.

That is, when the DMA control device 11 is configured as a single chip, there is a limit to the number of external pins, and how to reduce the number of pins becomes a serious problem.However, in the present invention, the number can be significantly reduced. Can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the data processing device of the present invention, and
The figure shows an embodiment conceptually showing the structure of a direct memory access control device, and FIG. 3 shows an explanatory diagram illustrating the bit structure of the word count register WCR shown in FIG. 2. In the figure, 1 is a central processing unit, 2 is a memory, and 3 to 10 are
11 is an input/output port section, 11 is a direct memory access control device, 12 is a bus switching circuit, 13 is a data bus line, 15
is a multiplexer, 16 is a decoder, 18 is a word count register, 19 is a subchannel counter, D
RQ represents a DMA request signal, and DOP represents a DMA operation permission signal.

Claims (1)

[Scope of utility model registration request] In a data processing device, at least a central processing unit and a plurality of one-chip input/output port units having the same configuration as a memory are connected to a data bus line, and the input/output port unit can directly access the memory. A one-chip direct memory access controller is provided for managing memory access control, and includes an m-ary counter, a word count register for indicating the mode of operation of the counter, and a direct memory for controlling the incrementation of the counter. - Provides an access instruction storage section, and further includes a selection means for scanning direct memory access control requests from the plurality of input/output port sections using the output of the m-adic counter contents outputted to an external pin, and selects the access instruction storage section. Means selects a direct memory access control request signal from each input/output port unit and causes the control device to generate the request, and the control device controls the instruction storage unit while executing the direct memory access control service based on the request. is set to stop incrementing of the m-adic counter, and selectively returns a direct memory access control response signal from the control device to the input/output port according to the contents of the counter; Depending on the mode of the operation instruction bit of the word count register mentioned above, the above response signal is returned, and after the actual direct memory access operation is completed, the m-adic counter restarts incrementing, or it is stopped as is. 1. A data processing device equipped with a one-chip direct memory access control device, characterized in that the input/output port unit continuously controls direct memory access.