JPS609882Y2 - digital correlator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital correlator that detects and processes correlation distances and correlation values between a standard digital pattern and a digital pattern to be tested using digital signals.

Figure 1 shows conventionally commonly used T
FIG. 2 is a block diagram of a digital correlator composed of DCIQQ4J and the like.

In the same figure, BIN is the standard digital pattern B1
．． B2...B6. This is a data input terminal for setting a 64-bit shift register consisting of
CK indicates a clock signal terminal of the shift register.

Similarly, AIN is A1. This is an input terminal of a 64-bit shift register composed of A2...A64.

The standard pattern is ``x*. When set in the shift register of B2...B64, A1. The signal changed to the signal) is terminal A.

Lo. It is set while scanning in synchronization with the clock applied to the

On the other hand, A□, N...A64 shift register and E%,
Each bit of the shift register B2a is subjected to an exclusive OR, and for example, when the polarities of both bits match, an output "1" is applied, and when they do not match, an output "0" is applied.

This output signal is converted into an analog signal by each bit D/A converter, added to all bit analog signals, and outputted to the output terminal C0UT.

Figure 2 shows the pattern to be inspected A□9 A2? This shows the waveform of the analog signal applied to the output terminal C0UT when it is passed to the A64 shift register.

In the same figure, at a constant reference voltage level ■A, terminal C3U
A when comparing the analog signal applied to T.

The length CL between 8 is the correlation distance, and the absolute value CV of one peak value
is the maximum correlation value (the value when it matches the most standard pattern)
It shows.

To find this correlation distance and maximum correlation value, use terminal C.
Since the signal applied to 0UT is an analog signal, it is processed using an ultra-high-speed A/D converter or a sample-hold circuit. Bad,
Furthermore, in order to operate at high speed, very expensive parts such as an A/D converter were required.

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, an object of the present invention is to provide a digital correlator that obtains correlation values and correlation distances by performing exclusive OR of each bit and then performing digital signal processing.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which reference numeral 100 denotes a clock signal A that is applied to an input data terminal ATN.

Lo. This is a shift register that shifts data in synchronization with each other, and input data is, for example, a signal obtained by converting a video signal shown by an ITV camera into a binary value.

101 is a register for storing a standard pattern, and the signal applied to the input terminal BIN is stored as B.

Store in synchronization with the LOCK clock signal.

EX is an exclusive OR circuit of each bit of the registers 100 and 101, and outputs logic "1" when the inputs match, and outputs logic "0" when they do not match.

Reference numeral 102 denotes an adder composed of a full adder circuit for calculating the number of output logic "1's" of the exclusive OR circuit.

This output signal has a predetermined value of V shown in FIG.
It is connected to the other input terminal B side of the first digital comparator 103 whose A side input terminal is the reference value corresponding to .

In other words, as shown in FIG.
Logic "1P" is output for the period from point A to point B, which is larger.

On the other hand, a clock signal Ac+ scans the pattern to be inspected.

. . Well, the gate circuit 1 performs the AND with the output signal of A≦B.
04, and this output signal is counted by a counter 105.

In other words, the counter 105 has the values from point A to point 3 shown in FIG.
The value of the correlation distance proportional to 3 (CL) is counted.

On the other hand, the output signal of the adder 102 is sent to the second digital comparator 107 (1) B input terminals and the primary buffer 1.
It is connected to the input data terminal of 06.

A number of input terminals of this second digital comparator 107 are connected to an output data terminal of the primary buffer 106.

Since the primary buffer 106 is a register with an initial value of O,
Output terminal A<B of second digital comparator 107
becomes logic "°1" when the correlation value becomes 0 or more, and this signal causes the primary buffer 106 to latch the output signal value of the adder 102.

Next, when the binary signal of the shift register 100 is shifted by 1 bit, it is compared with the previous value in the second digital comparator 107, and if A<B, a new correlator is transferred to the primary buffer 1.
Store in 06.

That is, the input data and the previous data are compared in magnitude, and if the values are larger, the contents of the primary buffer 106 are updated.

Therefore, as shown in FIG. 2, the maximum value CV of the correlation values is detected in the primary buffer 106.

According to the present invention, since correlation values are processed as digital signals, there is no need to consider deterioration of accuracy due to ground noise, noise contained in analog signals, etc., which has been a problem in the past.

In addition, when the scanning speed is high, the sample and
There is no need to use expensive parts such as hold circuits and A/D converters.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a conventional correlator, Fig. 2 is an output waveform diagram of the correlator for indicating correlation values and correlation distances, and Fig. 3 is a block diagram showing an embodiment of the present invention. be. In the figure, 100 is a shift register, 101 is a register, 102 is an adder, 103 is a first digital comparator, 104 is a gate circuit, 105 is a counter, 10
6 is a primary buffer, 107 is a second digital comparator, EX is an exclusive OR circuit, AIN and BIN are data input terminals, AC and L. G to QC Bcboc has clock signal terminal, C0LJ
T is a correlator output signal terminal, CL is a correlation distance, CV is a maximum correlation value, and ①A is a reference level.

Claims (1)

[Scope of utility model registration request] a register that stores a standard pattern; a shift register that shifts the pattern to be inspected in synchronization with a scanning signal; an adder that performs an exclusive OR of each bit of the register and the shift register and counts the output data; A first digital comparator that compares the output data of the adder with a preset reference value, and a counter that performs an AND operation between the output signal of the comparator and the scanning signal of the pattern to be inspected and counts the output result. a primary buffer that stores the output signal of the adder and the maximum value of the previous adder output signal; and a second digital buffer that compares the output value of the primary buffer with the output signal of the adder. A digital correlator comprising a comparator and digitally counting and determining correlation values and correlation distances between a standard pattern and a pattern to be inspected.