JPS6110228Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to an electronic timer clock that effectively utilizes conventional large-scale integrated circuits for clocks and enables the timer to operate for up to 24 hours. This prevents the once set timer operating time from being changed due to erroneous operation.

In recent years, recording of TV, FM radio, etc. while you are away has become popular, and this type of timer is increasingly desired. The situation is such that the above-mentioned requirements are not met in the case of the timer device.

In view of the above points, the present inventors have proposed an electronic timer device that makes effective use of conventional large-scale integrated circuits for clocks and allows the timer to operate for up to 24 hours. In other words, the timer operating time is set by two large-scale clock integrated circuits (LSI ₁ and LIS ₂ ) that have almost the same timer function, and the timer operating signal a generated from one integrated circuit LSI ₁ is output to the timer. Flip-flop circuit FFC for generation
When applied to the set input terminal SE, signal b is generated from this output terminal, and by operating the second large-scale integrated circuit LSI ₂ with this signal b, the timer function is started and the second The timer operation signal c generated from the integrated circuit LSI ₂ is sent to the reset input terminal RE of the flip-flop circuit FFC.
is applied to terminate the timer function. Identical parts in this conventional example and the present invention are designated by the same reference numerals.

However, in the device with the above configuration, the time set input terminals S, F, SEC of the second integrated circuit LSI ₂
(S: SLOW feed, F: FAST feed, SEC: seconds reset) can be operated externally, so the user may inadvertently press the time set terminals (S,
F, SEC) had the disadvantage that the initially set time would deviate.

In order to eliminate the above-mentioned drawbacks, this invention includes a first large-scale integrated circuit LSI ₁ for a watch, which generates a timer activation signal at a set time, and generates a timer activation signal after counting a predetermined time; A second large-scale integrated circuit LSI ₂ for clocks which has the same function as the circuit LSI ₁ and whose reset is canceled by a timer activation signal from this integrated circuit LSI ₁ , and a timer from the first integrated circuit LSI ₁ . In an electronic timer device comprising a timer output generation flip-flop circuit FFC that is reset by an activation signal and reset by a timer activation signal from the second integrated circuit LSI ₂ after a predetermined time has elapsed, the timer output generation flip-flop circuit A switching circuit SWC that is turned on and off by the output signal of the FFC is connected to the second time set input terminals S, F, and SEC.

An embodiment of this invention will be described below with reference to the drawings. LSI ₁ and LSI ₂ are large-scale integrated circuits for clocks that integrate time counter circuits and memory circuits (not shown). They generate a timer activation signal at a set time, and generate a timer stop signal after counting a predetermined time (59 minutes). It has a timer function to trigger the alarm. T.D.C.
are the display input terminals of the integrated circuits LSI ₁ and LSI ₂ above.
A display circuit for hours, minutes, and seconds is commonly connected to X ₁ and X ₂ via a display switching circuit GC.FFC is a flip-flop circuit for generating timer output, and the set input terminal SE and reset input of this flip-flop circuit FFC The above integrated circuits LSI ₁ and LSI ₂ are connected to terminal RE.
The timer out terminals TO ₁ and TO ₂ are electrically connected to each other. CLC ₁ is the second integrated circuit
A reset release circuit that normally holds LSI ₂ in the reset state and releases the reset state of the second integrated circuit LSI ₂ upon receiving a timer operation signal from the first integrated circuit LSI ₁ , for example, the switching transistor TR ₁ . , resistors R ₁ , R ₂ , diodes D ₁ to _{D 5}
The cathode sides of the diodes D ₁ to _{D 3} are electrically connected to the time set input terminals S, F, SEC (S is SLOW sending, F is FAST sending, SEC is second reset) of the integrated circuit LSI ₂ , respectively. The output terminal Q of the flip-flop circuit FFC is connected to the base pole of the switching transistor _TR1 . CLC ₂ is the reset release circuit mentioned above.
Operation switch P (P _{1 ,}
P ₂ , P ₃ ) and a resistor R ₃ , the second integrated circuit LSI ₂ is similar to the reset release circuit CLC ₁ .
It is electrically connected to the time set input terminals of S, F, and SEC.

SWC is a switching circuit inserted between the output side of the manual operation circuit CLC ₂ and the output terminal Q of the flip-flop circuit FFC, and includes a switching transistor Tr ₂ , a resistor R ₄ , diodes D ₅ , D ₆ , and D _{7 .} The ON/OFF operation is performed by the output signal of the flip-flop circuit FFC.

The output terminal Q and the inverted output terminal of the flip-flop circuit FFC are electrically connected to the timer off-in terminals TI ₁ and _{TI 2 of} the integrated circuits LSI 1 and LSI ₂ , respectively. RC is a relay circuit that opens and closes power to an electronic device (not shown) such as a radio.

Next, the operation of the above configuration will be explained.

The current time is 1:00, the time to start the timer is 2:00, and the time to end the timer is 5:00.
minutes. First, by operating a switch from the outside, the first integrated circuit LSI ₁ is made to store 2:00, and the second integrated circuit LSI ₂ is made to store 3 hours (5-2 hours).

At the set time of 2:00, the first integrated circuit
When a timer operation signal a is generated at the timer out terminal TO ₁ of LSI ₁ and this signal a is applied to the set input terminal SE of the flip-flop circuit FFC, an output signal b is output from the output terminal Q of the flip-flop circuit FFC. Ru. This output signal b is applied to the reset release circuit CLC ₁ , the relay circuit RC, the switching circuit SWC, and the timer off/on terminal TI ₁ of the first integrated circuit LSI ₁ . first integrated circuit
Output signal b to timer off/on terminal TI ₁ of LSI ₁
When is applied, the timing pulse of the integrated circuit LSI ₁ for a predetermined time (59 minutes) is wiped out.

On the other hand, the second integrated circuit LSI ₂ receives the voltage from the reset release circuit CLC ₁ until the set time 2:00.
Vc is applied to the time set input terminals S, F, and SEC and is held in the reset state. However, at the same time that the timer operation signal a is generated from the first integrated circuit LSI ₁ , the transistor Tr ₁ becomes conductive due to the output signal b from the flip-flop circuit FFC, and the voltage Vc is applied to the time set input terminal S. , F, SEC is no longer applied, the reset of the integrated circuit LSI ₂ is released and the clocking operation is started.

In the relay circuit RC, when the output signal b is applied, a relay (not shown) is activated to open (or close) the power supply of an electronic device such as a radio.

In addition, in the switching circuit SWC, the above signal b
The transistor Tr ₂ is in a non-conducting state before the voltage is applied, and the transistor Tr 2 of the second integrated circuit LSI ₂
FAST, SLOW, SEC can be operated by manual operation circuit CLC ₂ . However, the output signal b from the flip-flop circuit FFC makes the transistor _Tr2 conductive, and the function of the manual operation circuit _CLC2 is stopped and restricted. Therefore, during the timekeeping operation of the integrated circuit LSI ₂ , the SLOW, FAST, SEC switches P ₁ , P ₂ ,
Even if P ₃ is operated, integrated circuit LSI ₂ is not affected.

At 5:00, a timer activation signal c is generated at the timer out terminal _TO2 of the integrated circuit LSI ₂ , and this signal c is applied to the reset input terminal RE of the flip-flop circuit FFC. At this time, the signal d from the inverted output of the flip-flop circuit FFC turns off the timer of the second integrated circuit LSI ₂ .
This integrated circuit because it is applied to the on terminal TI ₂
Timing pulse P ₂ for a predetermined time (59 minutes) in LSI ₂
At the same time, the reset release circuit _CLC1 , relay circuit RC, and switching circuit SWC of the second integrated circuit LSI ₂ return to their original states. After the above process, the timer function is stopped.

In this device, if it is necessary to change the timer setting time while the timer function is operating,
When the release switch SW is opened, the switching circuit is activated.
The transistor Tr ₂ of the SWC can be cut off, and the operation switches P (P ₁ , P ₂ , P ₃ ) of the manual operation circuit CLC ₂ can be operated freely.

According to the device having the above configuration, when the timer operation signal a generated from the first integrated circuit LSI ₁ is applied to the flip-flop circuit FFC at a predetermined time, the signal is generated from the output terminal Q of the flip-flop circuit FFC. Since the switching circuit SWC is turned on by the output signal b to stop and restrict the function of the manual operation circuit CLC ₂ , once the timer operation time is set, there is no possibility that the user will accidentally operate the timer operation time. This has the practical effect that the timer operation time does not deviate even when the timer is operated.

[Brief explanation of the drawing]

The drawing is an electrical circuit diagram of an electronic timer device that is an embodiment of the present invention. LSI ₁ , LSI ₂ ...Large scale integrated circuit for watches, a...
...Timer activation signal from the first integrated circuit LSI ₁ ,
c...Timer operation signal from second integrated circuit LSI ₂ , FFC...Flip-flop circuit for timer output generation, b...Output signal of flip-flop circuit FFC for timer output generation.

Claims (1)

[Scope of utility model registration request] A first clock large-scale integrated circuit LSI ₁ that generates a timer activation signal a at a set time, and a first integrated circuit.
The second integrated circuit has almost the same function as LSI ₁ , and is reset by the timer activation signal from this integrated circuit LSI ₁ .
It is set by the timer operation signal a from the clock large-scale integrated circuit LSI ₂ and the first integrated circuit LSI ₁ , and is reset by the timer operation signal c from the second integrated circuit LSI ₂ after a predetermined time has elapsed. In an electronic timer device equipped with a flip-flop circuit FFC for generating a timer output, a switching circuit SWC that is turned on and off by the output signal b of the flip-flop circuit FFC for generating a timer output is connected to the second integrated circuit LSI ₂ . Electronic timer device connected to time set input terminals (S, F, SEC).