JPS6110253A - Semiconductor ic - Google Patents

Abstract

PURPOSE:To prevent wiring failure also at the maximum operating frequency without increasing wiring regions, by preparin two or more kinds of wiring widths by a method wherein wiring pitches different from basic wiring pitches of the wiring regions are prepared. CONSTITUTION:In a master slice semiconductor IC having a gate array structure which constitutes a desired logical circuit only in alteration of the wiring process by arranging a plurality of gate cells on a semiconductor chip, by providing a wiring region regulated in wiring channel lattice between gate cells, and then by connecting the arranged gate cells along the wiring channel lattice, wiring is carried out with the device having additionally wiring channel lattices different from basic wiring channel lattices with a suitable preparation of two or more kinds of wiring widths for drawing wirings on a wiring lattice according to the operating frequency of signal lines. For example, at low operation frequencies, wiring is carried out with wiring widths whereby reliability can be sufficiently secured. On the other hand, at high operating frequencies, wiring is carried out with wiring widths so that reliability can be secured over all signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and particularly to a master slice type semiconductor integrated circuit.

(Prior Art) Conventionally, a master slice type semiconductor integrated circuit has had a configuration as shown in FIG. That is, the internal cells include transistors and the like, and are regularly arranged in what are called internal basic cells 1 that can be realized as a certain functional gate. Further, between these internal basic cells, regions called intercell wiring regions 2 are arranged with regularity. In addition, an I10 block whose input/output buffer function is completely disabled and a chip terminal area 3 are arranged around the chip.

Basically, the element structure is such that a two-man NAND (or N0R) circuit, a three-man NAND (or N0R) circuit, etc. can be realized.

Further, in the inter-cell wiring region 2, wiring is performed along a wiring channel lattice having a certain basic wiring pitch both in the X direction and in the Y direction. Generally, a two-layer wiring structure is used in which a first metal wiring is provided in the X direction and a second metal wiring is provided in the Y direction. For both the first and second metal wirings, At or an At alloy is generally used.

With recent advances in microfabrication technology, it has become possible to realize semiconductor integrated circuits with high operating speeds by shortening the channel length of transistors, shallowly indenting diffusion layers, miniaturizing metal wiring, multilayer wiring, etc. ,Also, higher integration has progressed.

As the degree of integration increases, the complexity of circuits increases, and the wiring area also occupies a large area of money. Therefore, in order to reduce the wiring area and chip area, it is necessary to reduce the metal wiring width and spacing as much as possible. It was necessary to do some wiring.

At such a wiring pitch, wiring has begun to have a significant impact on the reliability of semiconductor integrated circuits that operate at high speed.

Let us now consider an 0MO8 master slice type semiconductor integrated circuit. FIG. 2 shows its internal basic cell, and FIG. 3 shows the entire logic circuit when this is made into a fully inverting circuit.

In FIG. 2, 11 is a gate polycrystalline silicon layer; 12 is a gate polycrystalline silicon layer;
source/drain regions of tiP channel transistors,
13 is a source/drain region of an N-channel transistor, and 14 is an extraction gate electrode. Further, in FIG. 3, 15 is an inverting circuit, and 16 is a load capacitor.

This circuit V has a rise time tr==2ns as an input waveform.
.

When operated at a frequency of IMHz with a pulse of falling time t (=2 ns), a current of 10 μA flows as the output charging/discharging current (Iy, Im). This charging/discharging current is , the charging and discharging current is proportional to the frequency, so a current of l,Q mA flows.

The wiring width of recent metal wiring is 2μ due to microprocessing.
Those with a width of m or less have also been put into practical use. In addition, because of multilayer wiring, the first layer wiring, which is wired closest to the 84 board, is generally made thin so that the second layer wiring does not break at the stepped portion, for example, the thickness 'tO, Regulations such as limiting it to less than 5μ will be necessary.

In this way, in a highly integrated, high-speed semiconductor integrated circuit where the wiring width is narrow and the wiring thickness must be thin, when operated at 100MHz as shown above, the frequency of 1.0
A current of mA flows, and its current density shows a value of 1×10'A/-.

Therefore, the wiring routed above it is 0 at the flat part.
, 5 μm thick becomes approximately 0.25 μm thin. When a current of 1.0 rrlA flows through such a location, the current density at that location exhibits a large value of 2xlO'A/cd.

Therefore, in conventional semiconductor integrated circuits, in order to ensure the reliability of the wiring, it is common to use a current density of 2×10'A/J or less for K, so if the metal wiring is thin at the step part, the metal wiring is overlapping. Considering all process variations such as thinning of the wiring due to etching, the current density is 1×105
It has the disadvantage that it is necessary to lower the operating frequency to below A/cfA, and the operating frequency cannot exceed 50 MHz. Furthermore, if the wiring pitch is increased and the wiring width is increased because the operating frequency is 150 MHz and 200 M1lz operation is possible, in a large-scale semiconductor integrated circuit, the wiring area becomes larger by the increased wiring pitch. When operating at 200MHz, the charge/discharge current of the gate output is 2mA, so if we consider factors such as thinning of the wiring at the step part and process variations, a wiring width of 8μm is required, compared to the conventional 2μm.
A wiring width four times the width of m is required.

Now, examples of wiring pitches are shown in FIGS. 4(a) and 4(b).

As shown in FIG. 4(a), if the width of the wiring 22 is 2 .mu.m, the dimension of the two contacts for one interval t is 2 .mu.m square, and the margin between the contact 23 and the wiring #j22 is 2 .mu.m, then the wiring pitch 21 is 6 .mu.m. In this example, the wiring width is 8μm.
As shown in Figure 4(b), the wiring 2
The wiring pitch 21' of 2' is 10 μm. Note that the dimensions of the contacts 23' are the same.

Therefore, if the wiring width is sufficient to ensure reliability even at the highest operating frequency, the wiring area will be 10/6 = 1.7
The disadvantage was that it was twice as wide, and the chip area was correspondingly larger.

(Object of the Invention) An object of the present invention is to enlarge the wiring area by preparing two or more types of wiring widths by preparing a wiring pitch different from the basic wiring pitch of the wiring area, in order to eliminate all of the above-mentioned defects. It is an object of the present invention to provide a highly reliable semiconductor integrated circuit which is free from wiring failures even at the highest operating frequency.

(Structure of the Invention) In the semiconductor integrated circuit of the present invention, a plurality of gate cells are arranged on a semiconductor chip, a wiring region defined by a wiring channel lattice is provided between the gate cells, and the arranged gate cells are connected to the wiring channel. In a master slice type semiconductor integrated circuit that includes a gate array structure in which a desired logic circuit is constructed by simply changing the wiring process by connecting along a lattice, the wiring channel lattice has two or more wirings with different dimensions. It consists of a channel lattice.

(Summary of the Invention) As described above, the semiconductor integrated circuit of the present invention has a wiring channel lattice different from the basic wiring channel lattice in addition to the basic wiring channel lattice. This can be done by appropriately preparing two or more widths.

In other words, at low operating frequencies, wires are wired with a wire width that ensures sufficient reliability (the normal minimum wire width is sufficient), and at high operating frequencies, wires are wired with a wire width that ensures reliability across all signal lines. Wiring should be done with a wide wiring width to ensure that. This provides a highly reliable semiconductor integrated circuit.

Furthermore, when a wiring area is defined by a wiring basic channel lattice (minimum wiring width and wiring spacing), the operating frequency is limited from the viewpoint of reliability. In addition, in order to ensure reliability even during the highest frequency operation, 1. If the wiring width is widened, the wiring cannot be drawn on the basic wiring channel grid, so it is necessary to make the basic wiring channel grid larger, so the same number of wiring channels is If an attempt is made to ensure this, the wiring area will increase by 1.7 times, as explained using FIG. 4, and the chip size will increase. However, by wiring the wiring with two or more types of wiring widths depending on the operating frequency of the signal line, the increase in the wiring area can be suppressed and the chip size can also be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a diagram showing a wiring channel grid according to an embodiment of the present invention.

This embodiment is an example in which two types of wiring grid pitches t-X1 and X2 in the X direction of the wiring channel are prepared, and one type of wiring grid pitch Y in the Y direction is prepared. In the figure, 31 is a wiring channel lattice with a pitch of X1, 32 with a pitch of X2, and 33 with a pitch of Y.

That is, in this embodiment, when executing an automatic wiring program that is a feature of the gate array, first use X2 and Y4, which have a wide wiring grid pitch and a large wiring grid pitch, to place wiring with a large wiring width on a high-speed signal line. Let's do it. Next, all the wiring with the minimum wiring width is performed using the basic wiring grid pitches X1 and Y.

Note that in the case of this embodiment, the wiring pitch is Xl:X.

Although the ratio is 2:3. Needless to say, this ratio is not limited to this.

(Effects of the Invention) As described in detail above, according to the present invention, since two or more wiring channel grids are provided with different dimensions, the wiring width can be adjusted according to the operating frequency of the signal line. Therefore, a highly reliable master slice type semiconductor integrated circuit without wiring failures even at its highest operating frequency can be obtained without increasing the wiring area as in the conventional case.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main parts of an example of a conventional master slice type semiconductor integrated circuit, Fig. 2 is a plan view showing an example of its internal basic cell, and Fig. 3 is an inverted version using the internal basic cell. The circuit diagrams of the circuit, FIG. 4(a) and Cb) are diagrams showing wiring examples having different wiring pitches, and FIG. 5 is a diagram showing a wiring channel lattice according to an embodiment of the present invention. 1... Internal basic cell, 2... Inter-cell wiring area, 3... Ilo block and chip, 7 terminal area, 11... Gate polycrystal silicon layer,
12.13...source/drain region, 14.
...Extraction gate electrode, 15...Inversion circuit, 16...Load capacitance, 21. 21'-...
・Wiring pitch, 22.22'...Wiring, 23.
23'...Contact, 31,32.33...
...Wiring channel grid, Xl, Xz, Y...
...Wiring pitch. Figure 67 Figure Z

Claims (2)

[Claims] (1) Arranging a plurality of gate cells on a semiconductor chip, providing a wiring region between the gate cells in which a wiring channel lattice is defined, and connecting the arranged gate cells along the wiring channel lattice to form a wiring line. A master slice type semiconductor integrated circuit having a gate array structure that configures a desired logic circuit only by changing a process, wherein the wiring channel lattice is composed of two or more wiring channel lattices with different dimensions. integrated circuit. (2) The semiconductor integrated circuit according to claim (1), wherein the dimensions of the different wiring channel grids are in an integer ratio to each other.