JPS61102767A - Driving method of semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which electrons are exchanged between two-dimensional electron gas (hereinafter referred to as 2DEG) layers generated at a plurality of hetero interfaces.

[Prior art and problems]

Conventionally, many types of semiconductor memory devices are known.

For example, MIS (metal 1nsulator
(semiconductor) non-volatile M that combines a field-effect transistor with a floating gate
Is memory and CMO3 (complementary
metal oxide semiconductor)
Dynamic RAM using dynamic RAM (dynamic r
andom access memory) or static RAM (static RAM)
dom access memory), etc. are known.

However, the non-volatile MIS memory requires high voltage or a long time for writing, and
M or static RAM has various drawbacks such as requiring a large number of elements, and overall, it can be said that it is still not in a satisfactory state in terms of speed.

[Purpose of the invention]

The present invention provides a semiconductor memory device that is capable of writing and reading faster than any conventional semiconductor memory device.

[Structure of the invention]

In the semiconductor memory device of the present invention, an n-type A7! Made of non-doped GaAs, which are stacked one above the other with a semiconductor barrier layer made of GaAs having a wide hunt gap and low electron affinity in between, forming a plurality of heterointerfaces with the semiconductor barrier layer. Two semiconductor layers and a non-contact layer provided on the upper semiconductor layer.
a doped Al2GaAs semiconductor layer, a gate electrode made of an Al vapor deposited film formed thereon, a first source/drain electrode made of gold/germanium/gold provided in contact with the upper hetero interface; Gold/germanium/germanium formed on the semiconductor barrier layer at the lower hetero interface
The structure is characterized in that it is equipped with second source/drain electrodes made of gold, and a control signal is applied to the electrodes so that electrons are exchanged between the two heterointerfaces.

The speed of electrons exchanged between the 2DEGri1 in this configuration is extremely high, and therefore writing and reading in this semiconductor memory device can be performed at high speed.

[Embodiments of the invention]

FIG. 1 is a cross-sectional side view of a main part of a semiconductor memory device according to an embodiment of the present invention.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs semiconductor layer, 3 is an n-type AfGaAs barrier layer, 4 is a non-doped GaAs semiconductor layer, and 5 is a non-doped GaAs semiconductor layer.
doped A/GaAs semiconductor layer, 6 and 7 are alloyed contact regions, 8, 9 are n+ type GaAsD contact layers, 1
0 and 11 are the first 2DEC layer and the second 2DIF, G
HlG is a gate electrode, Sl and S2 are source electrodes, Dl
and D2 is a drain electrode, BLI is a reading bit line, BL2 is a writing bit line, WL is a word line, and VS
L1 and VSL2 each indicate a single source line of constant potential (usually ground). This embodiment has the basic structure of the semiconductor memory device of the present invention.

In order to obtain the double Peter structure in this semiconductor memory device, MBC (molecular
By applying the ular beam epitaxy method, GaAs/n-A I! Ga
It is obtained by growing A s / G a As .

The source electrode St and the train electrode Dl, which are ohmic contact electrodes for the first 2DIEG layer 10, are formed by, for example, selectively regrowing the n+ type GaAs contact layers 8 and 9, and then applying, for example, a vapor deposition method thereon. Commonly used as money
It is obtained by forming an electrode made of germanium/gold (Au-Ge/Au).

The source electrode S2 and the drain electrode D2, which are ohmic and contact electrodes for the second 2DEGISN 11, are formed by selectively etching the periphery of the area where the electrodes are to be formed, and then using, for example, a vapor deposition method, to form Au-Ge/Au. The alloyed contact areas 6 and 7 are completed by forming and alloying a bottle of 1.

The gate electrode G is formed by depositing aluminum (,l).

FIG. 2 shows a semiconductor memory device according to an embodiment of the present invention shown in FIG.
FIG. 2 is an explanatory diagram of main parts showing a state in which electrons are exchanged between the 2DEC, JWIO, and the second 2DEGFil1.

FIG. 3 is an energy band diagram under the gate electrode in the non-biased state of the embodiment of the present invention, which is more in line with the structure actually used than the embodiment explained with reference to FIG. Because of this, the structure is more specific.

In the figure, 21 is the upper electrode of AZ, 22 is a non-doped Δ1o with a thickness of about 500 mm, 3
G a O,7AS semiconductor layer, 23 has a thickness of ~100
(person) non-doped GaAs semiconductor layer, 2
4 is a non-doped Aeo with a thickness of about 60 [people]
,, Ga, 7A s semiconductor layer, 25 has a thickness of 100
[person]'s n-type AI Ga AS semiconductor layer, 26 has a thickness of 200 [person]'s non-doped A lo, * Ga
o, 7 A s semiconductor layer, 27 is n of thickness 60 [in]
type A lo, s G a o, 7 A S semiconductor layer,
28 is a non-doped A l O,3 with a thickness of 60 mm.
Gao, 7 semiconductor layers, 29 is a non-tope GaAs semiconductor layer with a thickness of 6000 (people), 30 is the second 2DEG
layer (in FIG. 1, the second 2DEG layer 11 (target) is shown respectively. In addition, the n-type AI!Ga
The barrier portion corresponding to the As barrier layer 3 is a non-doped Ap, 61G ao7A s semiconductor layer 24, and an n-type A
eo, Gao7A s semiconductor layer 25, non-doped A f103c ao, 7A s semiconductor layer 26, n-type A
7! . , 3G a (,,,, As semiconductor layer 27 and non-doped A I16.q Ga O,7A s semiconductor layer 28.

In FIG. 3, when the semiconductor memory device is non-biased, the first 2DEGFi is not formed; therefore, the first 2DEGFi is not formed.
The upper channel shown in the figure is in a non-conducting state, i.e.
This is an example of what is turned off.

The case of writing in the embodiment described with reference to FIG. 3 will be described with reference to FIG. 4.

FIG. 4 is an energy hand diagram near the barrier portion during writing, and the same portions as those explained in connection with FIG. 3 are indicated by the same symbols.

In the figure, 31 indicates the first 2DEG layer, and 32 indicates the barrier portion.

Now, as seen in the figure, the gate electrode 21 (Il electrode is applied) and the source electrode and the drain electrode (the source electrode S2 and the train electrode in FIG. (corresponding to D2) by applying an electric field between them.

That is, some electrons in the second 2DEC 530 are accelerated and heated by the electric field between the source electrode and the drain electrode, and Aj! The kinetic energy exceeding ~0.3 (e■), which is the potential barrier of GaAs, is obtained iυ
However, the other electrons are attracted by the electric field caused by the gate voltage ti21 and fall into the channel at the top 1, which is the side closest to the gate electrode 2I, where they form the first 2DEG 231.
Yes, the writing has now been done.

The time required for this writing is: ■ Second 2DEC'? ! The time required for some of the electrons in 30 to become hot J is 1 ■ The hot electrons form Barry 1/portion 32 ∆l! G 2 , the time τ for drifting in S
2, but for the above (■), the second 2DEG layer 3
Considering that the carrier mobility at zero is extremely high and scattering is difficult to occur, it can be regarded as approximately the acceleration of free electrons, and is given by: Here, e=1.6X10 (C) m=o, 067X9. lX1O (Kg), and
The electric field E is such that the distance between the source electrode and the drain electrode is 2.5 [μm] and the voltage applied therebetween is l (V).
4 X l O (V/m).

The velocity V of electrons corresponding to kinetic energy exceeding 0.3 (eV), which is the potential barrier in AlGaAs, is approximately 10 (m/sec), and from the above data,
As the time τ required to make the electron hot, τ1 = IX10 (seconds) = 1 (p seconds) is obtained.

Also, the time 1°2 required for electrons to travel in ARGaAs in the barrier portion 32 due to drift is:
It is known that when the electric field is about 10 (V/m), it is less than 1 p second.

Therefore, the potential at the gate electrode 21 is set as follows: ~0.1 (, crm) x 10 (V/m)=0
．． 1 [V) (0.1 Cμm]: Distance from the gate electrode 21 to the lower channel) By keeping the voltage at a certain level, the electron transit time τ here can be reduced.
2 can also be made less than 1 (p seconds).

Combining the above results, the time required for writing is τ1
+τ2<2 (p seconds), which is extremely short.

Figure 5 shows the energy near the barrier part in the memorized state.
This is a hand diagram, and the same parts as those described with reference to FIGS. 3 and 4 are designated with the same symbols.

In the figure, E9 is the Fermi level at the gate,
EFi indicates the Fermi level in the first 2DEC layer 31, and Epz indicates the Fermi level in the second 2DEGP 530. Furthermore, Er−z=E'p
It is 6.

In the memory state, the bias voltage applied during writing is completely removed, and the potential in the upper channel, and thus in the first 2DEG layer 31, decreases due to the influence of the N-multiplied charges, that is, the potential in the first 2DEG layer 31 decreases to the Fermi level. E is rising.

In the memory state, due to the presence of the first 2DEC layer 31, the source electrode and drain electrode (
Source electrode 1A Sl and drain electrode D1 in FIG.
(equivalent to)) there is continuity between them.

Therefore, in order to perform reading in this semiconductor memory device, (1) the source electrode and the drain electrode corresponding to the source electrode S1 and the drain electrode DI are connected to the source electrode and the drain electrode corresponding to the source electrode S2 and the drain electrode D2, and the gate electrode is 21, and conduction between the source electrode and the drain electrode corresponding to the source electrode Sl and the drain electrode (if) is detected.

(2) Detecting the potential difference between each source electrode corresponding to source electrodes S1 and S2. For example, a high-impedance voltmeter may be connected between each source electrode.

One method is possible.

FIG. 6 is an energy band diagram near the barrier portion during erasing of written information, and the same portions as those explained in connection with FIGS. 3 to 5 are indicated by the same symbols.

The operation in this case is completely opposite to the writing operation, and a voltage is applied between the source electrode and the train electrode corresponding to the source electrode Sl and the drain electrode Di, and the first 2DEC layer 3
Make the electrons at 1 hot. 1st 2DEC; 53
An electric field exists in the barrier portion 32 while electrons are accumulated in the second 2DE (J30), and the hot electrons are lifted toward the second 2DE (J30).The time required for erasing is slightly longer than the time required for writing. It's longer, but about the same amount.

As can be seen from the above description, in this semiconductor memory device, the time required for writing or erasing is, even if roughly estimated, less than 10 [p seconds], which is an extremely short time.

By the way, when manufacturing the embodiment described with reference to FIG. 1, the selective regrowth technique was used, but the semiconductor memory device according to the present invention does not require the application of such a special technique. It is also possible to manufacture

FIG. 7 is a cross-sectional side view of essential parts of an embodiment that can be manufactured by applying the continuous growth method, and the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

In the figure, 41 is a p+ type GaAs buried layer, and 42 is tin (Sn) formed by continuous growth on the n type AfGaAs semiconductor layer 5, for example ~l x l O1? (cm
-' ) topographic n'' type GaAs semiconductor layer, 4
3 indicates an alloyed region, and BG indicates a hack gate bias electrode.

Source electrode SL and drain electrode Di in this example
The formation of ALI-Q on the n+ type GaAs semiconductor layer 42
It is formed each time an electrode material such as E or Au is broken. Note that at this time, no alloying heat treatment is performed.

Gate 1 excavation G is the area where the gate electrode is to be formed.
The + type GaAs semiconductor layer is removed by etching.
Al is deposited on a part of the surface of the exposed n-type AllGaAs semiconductor layer 5.

Regarding the source electrode S2 and the drain electrode D2, the first
As in the embodiment shown in the figure, alloying treatment is performed for 1"r.

In the embodiment shown in FIG. 1, the gate voltage during writing is applied to the channel between the gate electrode G and the source electrode 2 and drain electrode D2, and in this case, between the source and drain, 2DEGFi Because of the high electrical conductivity (~100 [Ω/port]) caused by the high electron mobility of There is a possibility that not enough bias is applied between the channels.

In order to avoid such problems, in the embodiment shown in FIG. 7, a p+ (or n+) type GaAs buried layer 41 is formed and a back gate bias is applied.

In this case, in order to draw out the bank gate bias electrode BG, if it is a p-type back gate, select electrode material,
That is, alloying may be performed using Au-zinc (Zn) that forms ohmic contact with only the p-type semiconductor. still,
In the case of a mouth-shaped hack gate, it is necessary to separate the bank gate bias electrode BG from the second 2DEC layer 30 by some means.

Figures 8 (fal to fd) show n-type A for separating two 2DEGFi in the embodiment explained with reference to Figure 1.
l! FIG. 3 is a diagram showing a modification of a barrier portion made of GaAs, and is shown in the form of an energy band diagram with the bending of the hand omitted for simplicity. Note that the same parts as those explained with reference to FIG. 1 are indicated by the same symbols.

In each figure, the portions hatched with broken lines are doped with silicon (Si). 6/! A GaAs semiconductor layer is shown, and the direction of the arrow is the upper side, that is, the direction of the gate electrode.

FIG. 8 (al) is an example in which the Si-doped AlGaAs semiconductor layer 3 is separated significantly from the upper hetero-interface, so that, for example, about 300 people can pass through it.

Figure 8 (bl is 2D from the hetero interface other than barrier layer 3)
This is an example in which EC is supplied.

Figure 8 (C1 is A RXG al-zA for electron supply)
A ji! with a higher AJ composition ratio than the s semiconductor layer! y G
By using the a1□Human S semiconductor 5 (y>x) as a buffer layer, leakage of accumulated charges that become stored information is further reduced.

Figure 8 (dl is an AβQaAs semiconductor layer with a linearly varied X value, so-called a graded layer is used to increase the drift speed of hot electrons during writing and reduce the writing time. This is an example.

(Effects of the Invention) In the semiconductor memory device of the present invention, a semiconductor barrier layer having a wide band gap and low electron affinity is laminated on a substrate with a semiconductor barrier layer sandwiched therebetween, and a plurality of A plurality of semiconductor layers forming interfaces and a two-dimensional electron gas layer generated near the plurality of hetero-interfaces and exchanging electrons via the semiconductor barrier layer. The structure includes an electrode associated with a dimensional electron gas layer.

By adopting this configuration, it is possible to write information+a by exchanging electrons between the 2DEGFi through the semiconductor layer with a wide band gap, and the 2DEGFi can write information.
Written information, ie, information can be read by detecting the presence or absence of accumulated charge from the electrode that contacts DEGFi. Then, the 2D of this configuration
The speed at which electrons are exchanged between IEG layers is extremely high, and therefore it is possible to obtain a semiconductor memory device that can be read and written at extremely high speed.

[Brief explanation of drawings]

FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, FIG. 2 is an explanatory diagram of essential parts showing a state in which electrons are exchanged between ZDBGPs in the embodiment shown in FIG. Figure 3 is an energy hand tire diagram under the gate electrode in another embodiment of the present invention, and Figure 4 is for explaining the case of writing in the embodiment explained in Figure 3. Figure 5 is an energy hand diagram near the barrier part, and Figure 6 is an energy hand diagram near the barrier part for explaining the storage state.
The figure shows the energy hand in the vicinity of the barrier part to explain the case of reading the written information.
FIG. 7 is a cross-sectional side view of essential parts of another embodiment of the present invention, and FIGS. Each shows a hand diagram. In the figure, ■ is a semi-insulating GaAs substrate, 2 is a non-doped (:, afi, s semiconductor layer, 3 is an n-type Aj!Ga
As barrier layer, 4 is non-doped GaAs semiconductor layer,
5 is a non-toped ARGaAs semiconductor layer, 6 and 7 are alloyed contact regions, and 8 and 9 are n-type GaAs contact layers. 10 and 11 are a first 2DEG layer and a second 2DEG layer, G is a gate electrode, Sl and S2 are source electrodes, Dl and D2 are drain voltages li, BL1 is a read bit line, BL2 is a write bit line, WL is word line, VS
LI and VSL2 each indicate a power supply line with a constant potential. Figure 1 Figure 2 Figure 4 Figure 7 Figure 8 (a) (b) (C) (d)

Claims (1)

[Claims] A semiconductor barrier layer made of n-type AlGaAs with a wide band gap and low electron affinity is stacked on top of a semi-insulating GaAs substrate with a semiconductor barrier layer sandwiched therebetween, and a plurality of hetero interfaces are formed between the semiconductor barrier layer and the semiconductor barrier layer. two semiconductor layers made of non-doped GaAs to be formed; a non-doped AlGaAs semiconductor layer provided on the upper semiconductor layer; a gate electrode made of an Al vapor deposited film formed thereon; a first source/drain electrode made of gold/germanium/gold provided in contact with the hetero interface of;
The lower hetero interface is provided with second source/drain electrodes made of gold/germanium/gold formed on the semiconductor barrier layer so that electrons are exchanged between the two hetero interfaces. A semiconductor memory device characterized in that a control signal is added to the semiconductor memory device.