JPS61102831A - Waveform equalization system pull-in control method - Google Patents

Waveform equalization system pull-in control method

Info

Publication number
JPS61102831A
JPS61102831A JP22396784A JP22396784A JPS61102831A JP S61102831 A JPS61102831 A JP S61102831A JP 22396784 A JP22396784 A JP 22396784A JP 22396784 A JP22396784 A JP 22396784A JP S61102831 A JPS61102831 A JP S61102831A
Authority
JP
Japan
Prior art keywords
signal
equalizer
data
agc circuit
control method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22396784A
Other languages
Japanese (ja)
Inventor
Kazuhiko Takaoka
高岡 和彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22396784A priority Critical patent/JPS61102831A/en
Publication of JPS61102831A publication Critical patent/JPS61102831A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/04Control of transmission; Equalising

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、トレーニング信号を用いて、同期引込みする
自動等化器内蔵の復調器に関し、特にトレーニング信号
をもちいるシステムの等化器の引込み時間を短縮しうる
自動等化器の引込み制御方式に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a demodulator with a built-in automatic equalizer that performs synchronous pull-in using a training signal, and in particular to a demodulator with a built-in automatic equalizer that performs synchronous pull-in using a training signal. This invention relates to a pull-in control method for an automatic equalizer that can shorten the time.

〔発明の背景〕[Background of the invention]

従来の波形等化システムは、特公昭55−33203号
公報に記載のように、等化残信号に基づき補正信号を補
正する自動等化法においては、初期引込み時の調整係数
確立に、トレーニング信号を用いている。このため同期
するためある一定の時間が必要とし、早い立上りを要求
するシステムの適用が困難であった。
In the conventional waveform equalization system, as described in Japanese Patent Publication No. 55-33203, in the automatic equalization method that corrects the correction signal based on the equalized residual signal, the training signal is used to establish the adjustment coefficient at the initial pull-in. is used. For this reason, a certain amount of time is required for synchronization, making it difficult to apply a system that requires a quick start-up.

すなわちトレーニング信号は、一般に情報データの波形
を等化する前、すなわちデータの直前に配置されるもの
で、復調器の初期化および引込みが行われる。第1図(
α) 、 fblは、トレーニング信号の初期化を説明
する図、第2図は、従来の自動等化システムのブロック
図である。第1図(α)は、受信信号の位相平面を示し
A、B、・・・は、データを示すもので、第1図(b)
の各データA B CDと対応するものであろう トレーニング信号は、無信号期間N OX M T 。
That is, the training signal is generally placed before the waveform of the information data is equalized, that is, immediately before the data, and the demodulator is initialized and pulled in. Figure 1 (
α) and fbl are diagrams for explaining initialization of a training signal, and FIG. 2 is a block diagram of a conventional automatic equalization system. Fig. 1 (α) shows the phase plane of the received signal, and A, B, . . . show data, and Fig. 1 (b)
The training signal that would correspond to each data A B CD is the non-signal period NOX M T .

第1図体)図示のデータA、Bが規則的く交互に繰返さ
れる期間(以下AB期間:ALT)、データCDがある
一定の成虫多項式であられされランダムに繰返される期
間(以下CD期間:AE)、および位相平面上に存在す
る全てのデータかランダムに配置されるスクランブルデ
ータ区間により構成されデータの直前に配置される。
1st figure) A period in which the illustrated data A and B are regularly repeated alternately (hereinafter AB period: ALT), a period in which data CD is arithmetic with a certain imago polynomial and randomly repeated (hereinafter CD period: AE) , and all the data existing on the phase plane are randomly arranged scramble data sections, which are arranged immediately before the data.

第1図(、Zl(,51によって、第2因のブロック図
の引込入動作を説明する。
The drawing-in operation of the block diagram of the second factor will be explained using FIG.

1、 データが入力されない場合1等化器4のタップ係
数はイニシャライズされ、1のAGC回路が最小レベル
信号を検出すべき利得に設定される。
1. When no data is input, the tap coefficients of the 1 equalizer 4 are initialized, and the AGC circuit 1 is set to a gain that should detect the minimum level signal.

2、 次1cAB期間の信号ABAB・・が入力される
と5のレベル検出器がレベルを検出し、1のA G C
設定利得値により、6の制御回路が現在の入力レベルを
計算し高速度(標準レベル出力となる様設定する。これ
は等化器が調整される前に、入力レベルを一定にし初期
タイミング誤差および初期周波数オフセクト誤差の補正
を行うために必要である。
2. When the signal ABAB... for the next 1cAB period is input, the level detector 5 detects the level, and the A G C
Depending on the set gain value, the control circuit at 6 calculates the current input level and sets it to a high speed (standard level output). This is done by keeping the input level constant and eliminating initial timing errors and This is necessary to correct the initial frequency offset error.

3、 キャリア、タイミング初期が最適となり、トレー
ニング信号がAB傷信号らCD信号に移行すると、等化
器4の引込み動作が前出の2値不規則に配置されたデー
タ群(PN符号)によって行われる。
3. When the carrier and timing are optimal at the initial stage and the training signal shifts from the AB defect signal to the CD signal, the pull-in operation of the equalizer 4 is performed using the aforementioned binary irregularly arranged data group (PN code). be exposed.

4、つづいてスクランブル期間の多値ランダム信号が、
等化器4に入力され、2値ランダムデータによって収束
したタップ係数をさらに更新し、争めのこまかい等化を
行う。
4. Next, the multi-level random signal during the scrambling period is
The tap coefficients input to the equalizer 4 and converged with binary random data are further updated to perform fine-grained equalization.

以上1〜4によるトレーニング信号を使用して引込みを
完了させ以降はデータにより波形等化を行う。このとき
AGC回路は、AB期初期に高速にプリセントされた初
期設定レベルを長い時定数で更新する定常AGCと動作
する。
The training signals 1 to 4 above are used to complete the pull-in, and thereafter waveform equalization is performed using the data. At this time, the AGC circuit operates as a steady AGC that updates the initial setting level that is presented at high speed at the beginning of the AB period with a long time constant.

本構成で使用される等化器は、補正信号を等化残信号と
タップ出力即ち復調後のベースノ(ンド信号の所定間隔
の信号成分とくより制御するMS法(Minimam 
mean 5quare Method )の自動等化
器が使用される。補正信号すなわちタップ利得はトレー
ニングにて与えられる当該PN符号が正しく等化出力し
得るまで等化係数を補正するためかなりの時間を費する
欠点をもっている。
The equalizer used in this configuration uses the MS method (minimum control method) in which the correction signal is controlled by the equalized residual signal and the tap output, that is, the signal components at predetermined intervals of the base node signal after demodulation.
An automatic equalizer with a mean 5quare Method is used. The correction signal, that is, the tap gain, has the disadvantage that it takes a considerable amount of time to correct the equalization coefficient until the PN code given during training can be correctly equalized and output.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、以−ヒの欠点を取り除くよう等化器を
高速に設定できる波形等化システムを提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a waveform equalization system that can quickly set the equalizer so as to eliminate the following drawbacks.

〔発明の概要〕[Summary of the invention]

本発明は、トレーニング信号とデータ信号をキャリア信
号で変調した信号を受信し、AGC回路(てより振幅を
一定にし、復調徒歩なくともデータ信号期間の信号波形
を等化する等化器を具備するデータ復調器において、該
トレーニング信号の無信号に続くデータ点配置図ヒでの
2点間交互繰返し信号により該AGC回路を高速に初期
設定する手段と、該交互繰返し信号に続く2点間ランダ
ム繰返しの等化器調整信号を検出して、再度AGC回路
の初期値が等化器調整ゲインが等制約に大きくなる様設
定することにより、後位の自動等化器の立上り時間およ
び確立を向上させることを特徴とするものである。
The present invention receives a signal obtained by modulating a training signal and a data signal with a carrier signal, and is equipped with an equalizer that makes the amplitude constant using an AGC circuit (an AGC circuit) and equalizes the signal waveform of the data signal period without demodulation. In a data demodulator, means for quickly initializing the AGC circuit by a two-point alternating repeated signal at a data point constellation diagram H following no signal of the training signal, and a two-point random repeating signal following the alternating repeating signal. By detecting the equalizer adjustment signal and setting the initial value of the AGC circuit again so that the equalizer adjustment gain is large to the same constraint, the rise time and establishment of the subsequent automatic equalizer are improved. It is characterized by this.

〔発明の実施例〕[Embodiments of the invention]

以下、第3図に本発明の一実施例のブロック図を示し1
本図を用いて詳述する。図中、第2図に用いたものは同
一の記号で示しである。次に第1図の(′B)を用いて
、第3図の動作を説明する。無信号時は従来例と同一で
ある。AB信号期間も同様に、レベル、タイミング、キ
ャリア補正がなされ1等化器の調整準備が完了する。
Below, a block diagram of one embodiment of the present invention is shown in FIG. 1.
This will be explained in detail using this figure. In the figure, those used in FIG. 2 are indicated by the same symbols. Next, the operation in FIG. 3 will be explained using ('B) in FIG. When there is no signal, it is the same as the conventional example. Similarly, level, timing, and carrier corrections are performed during the AB signal period, and preparations for adjustment of the equalizer are completed.

トレーニング信号がABからCD期間に移行すると、等
化器の引込みが開始される。この切り換わり点は、7の
ABCD期間検出器九より検出される。この時点でAG
C値は、初期設定値の2〜3倍の値とするうその後のA
GC回路はある一定の時定数にて、最適レベルへと更新
する定常AGC@作を行う。この結果、自動等化器の調
整ゲインは等制約忙、調整初期大きく、AGC値が設定
値に近ずくと定常値におちつくことになり1等化器の初
期引込み時間の短縮が可能となり引込み後は、調整ゲイ
ンが小さくなり、安定化される。
When the training signal transitions from AB to CD period, equalizer pull-in begins. This switching point is detected by the ABCD period detector 9 of 7. At this point AG
The C value should be 2 to 3 times the initial setting value.
The GC circuit performs steady AGC @ operation to update to the optimum level at a certain time constant. As a result, the adjustment gain of the automatic equalizer is busy with equal constraints, and is large at the beginning of adjustment, but as the AGC value approaches the set value, it settles to a steady value, which makes it possible to shorten the initial pull-in time of the equalizer, and after the pull-in. , the adjustment gain becomes smaller and stabilized.

すなわち、等化器としてトランスバーサルフィルターの
タップ調整アルゴリズムは下式となるC  (N+ 1
 ) :y−−t −X K −JN本式では、両側波
帯変調の信号はベクトルで表現している。Kはタップ調
整係数で、入力信号の相関をとって調整される。 はデ
ータ入力信号、 は誤差信号である。また?は調整ゲイ
ンである。と式からAGC設定レベルを可変することは
、?の値が変化したことに相当し、初期2が大片く、し
だいに設定値となることが実現できるためである。
In other words, the tap adjustment algorithm of the transversal filter as an equalizer is as follows: C (N+ 1
) :y--t-X K-JN In this formula, the signal of double side band modulation is expressed by a vector. K is a tap adjustment coefficient, which is adjusted by taking the correlation of the input signal. is the data input signal and is the error signal. Also? is the adjustment gain. Is it possible to vary the AGC setting level from the formula? This corresponds to a change in the value of , and it is possible to realize that the initial value 2 gradually becomes the set value.

〔発明の効果〕〔Effect of the invention〕

以−ヒ記載した様に、本発明によれば、等化器の調整ゲ
インをAGC回路により等価的に可変することにより、
引込み時間の短縮化および、引込み後のゲインを小さく
できるため安定後の等化ハズレ等が防上でき、同期確立
が向上する効果を奏する。また、等化器のリード追加な
して、AGCの設定のみで可変ゲインが可能となる。
As described below, according to the present invention, by equivalently varying the adjustment gain of the equalizer using the AGC circuit,
Since the pull-in time can be shortened and the gain after the pull-in can be made small, equalization loss after stabilization can be prevented, and synchronization establishment can be improved. Further, variable gain can be achieved only by setting the AGC without adding an equalizer lead.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(α)(h)は、等化器内蔵のデータ復調器の引
込み動作の説明図、第2図は、従来の等化量内蔵復調器
のブロック図、第3図は、本発明の一実施例の波形等化
システムのブロック図である。 l・・・AGC回路、    5・・・レベル検出器6
・・・制御回路。 ゝ\〜−−′
Fig. 1 (α) and (h) are explanatory diagrams of the pull-in operation of a data demodulator with a built-in equalizer, Fig. 2 is a block diagram of a conventional demodulator with a built-in equalization amount, and Fig. 3 is a diagram of the present invention. 1 is a block diagram of an example waveform equalization system; FIG. l...AGC circuit, 5...level detector 6
...Control circuit.ゝ\〜−−′

Claims (1)

【特許請求の範囲】[Claims] 1、トレーニング信号とデータ信号をキャリア信号で変
調した信号を受信し、AGC回路により振幅を一定にし
、復調後少なくともデータ信号期間の信号波形を等化す
る等化器を具備するデータ復調器において、該トレーニ
ング信号の無信号に続くデータ点配置図上での2点間交
互繰返し信号により該AGC回路を高速に初期設定する
手段と、該交互繰返し信号に続く2点間ランダム繰返し
の等化器調整信号を検出して、再度AGC回路の初期値
が等化器調整ゲインが等価的に大きくなる様設定するこ
とにより、後位の自動等化器の立上り時間および確立を
向上させることを特徴とする波形等化システムの引込み
制御方式。
1. A data demodulator that receives a signal obtained by modulating a training signal and a data signal with a carrier signal, makes the amplitude constant by an AGC circuit, and includes an equalizer that equalizes the signal waveform of at least a data signal period after demodulation, Means for quickly initializing the AGC circuit by an alternately repeating signal between two points on a data point constellation diagram following no signal of the training signal, and equalizer adjustment of random repeating between two points following the alternatingly repeating signal. By detecting the signal and setting the initial value of the AGC circuit again so that the equalizer adjustment gain becomes equivalently large, the rise time and establishment of the subsequent automatic equalizer are improved. Entrainment control method for waveform equalization system.
JP22396784A 1984-10-26 1984-10-26 Waveform equalization system pull-in control method Pending JPS61102831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22396784A JPS61102831A (en) 1984-10-26 1984-10-26 Waveform equalization system pull-in control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22396784A JPS61102831A (en) 1984-10-26 1984-10-26 Waveform equalization system pull-in control method

Publications (1)

Publication Number Publication Date
JPS61102831A true JPS61102831A (en) 1986-05-21

Family

ID=16806489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22396784A Pending JPS61102831A (en) 1984-10-26 1984-10-26 Waveform equalization system pull-in control method

Country Status (1)

Country Link
JP (1) JPS61102831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825570A (en) * 1994-03-18 1998-10-20 Fujitsu Limited PRML regenerating apparatus having reduced number of charge pump circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825570A (en) * 1994-03-18 1998-10-20 Fujitsu Limited PRML regenerating apparatus having reduced number of charge pump circuits
US5841602A (en) * 1994-03-18 1998-11-24 Fujitsu Limited PRML regenerating apparatus
US5847891A (en) * 1994-03-18 1998-12-08 Fujitsu Limited PRML regenerating apparatus
US6002538A (en) * 1994-03-18 1999-12-14 Fujitsu, Ltd. PRML regenerating apparatus having adjusted slice levels

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