JPS61107444A - Error trace system - Google Patents

Abstract

PURPOSE:To obtain an error generating time with high accuracy by providing a common timer having higher accuracy than that of a system timer to a memory control section and obtaining the time information for error trace information from the common timer. CONSTITUTION:The common timer 41 of the memory control section 40 has higher accuracy than the system clock and when a system power is applied, the timer 41 counts time in synchronization with the oscillated period of an oscillator 43 and gives a time after system start. A processor 51 increment s the content of a timer value storage area 55 in an RAM 33 by 1 every time timer interruption takes place to a microprocessor 51 from a timer 52 of an input/output processor 50. When the input/output processor 50 detects an error during data processing, the processor 51 generates a timer read command to the memory control section 40 and a timer value of the timer 41 is read in a data register 54 via a DMA bus 80. The error trace information comprising the timer value of the register and error information is stored in an area 56 in the RAM53 and stored in a main memory 30 via the bus 80 and used for fault analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an error tracing method when an error is detected during data processing in an input/output processor.

[Technical Background of the Invention] As shown in FIG.
In a computer system interconnected by a computer system, error tracing when an error is detected during data processing in the input/output processor 13 is generally performed as follows. First, the input/output processor 13 stores error information (memory read error/DMA bus transfer parity error) in the status storage area on the main memory 12, and
Interrupt p u 1i with I. As a result, the CPU ii stores error trace information consisting of time information indicating the time when an interrupt was received from the input/output processor 13 and error information in the status storage area in the trace area on the main memory 12. Store. The CPU 11 then performs failure analysis based on the trace information stored in the trace area on the main memory 12.

[Problems with Background Art] The above-mentioned time information is generally obtained by counting timer interrupts from the 50m5 system timer 15. Therefore, the time that can be specified by the system timer 15 is an integral multiple of 50m5. Therefore, if two input/output processors 13.13 fail in the same soms, the error occurrence times will be the same.

In such a case, there is no problem if the failure locations of the input/output processors 13.13 are unrelated to each other, but for example, if the DMA
When a secondary failure occurs due to failure of a bus interface element, there is a drawback that it is impossible to determine which is the primary cause. Furthermore, if the memory write function of the input/output processor 13 is not normal, there is also a drawback that error trace information cannot be collected.

[Object of the Invention] This invention has been made in view of the above circumstances, and its purpose is to provide a common timer with higher accuracy than the system timer in the memory control unit, and to collect time information, which is a component of error trace information, from the common timer. An object of the present invention is to provide an error tracing method that can accurately determine the time when an error occurs by obtaining the timer value, thereby improving the accuracy of failure analysis.

Another object of the present invention is to provide an error tracing method that can trace the time of error occurrence even when time information (timer value) cannot be obtained from a common timer.

Still another object of the present invention is to provide an error tracing method that allows error analysis even when error tracing to main memory is impossible.

[Summary of the Invention] According to the present invention, in a computer system in which a CPLI, a main memory, and an input/output processor are interconnected by a DMA bus, a common timer having a higher frequency than a system timer is provided in a memory control section of the main memory. It will be done.

The timer value indicated by this common timer is used when an error is detected during data processing in the input/output processor.
The timer value is read out to the input/output processor via the A bus, and error trace information consisting of the timer value and error information is generated. The error trace information generated in this way is
Traced to main memory via MA bus.

[Embodiment of the Invention] FIG. 1 shows a computer system according to an embodiment of the invention. In the figure, 20 is a CPU, 30 is a main memory, 4
0 is a memory control section of the main memory 30.

In the memory control unit 40, 41 is the system time (50
A common timer 42 is a data register used for exchanging data between the main memory 30 and a DMA bus 80, which will be described later. Common tie
741 includes an oscillator 43 that oscillates with a period of several tens of μs,
The counter 44 performs a counting operation in synchronization with the output signal from the oscillator 43. The counter 44 becomes ready for counting in response to a power-on signal 45 that transitions to a low level when the system power is turned on.

50, 50, . . . are input/output processors. The input/output processor 50 includes a microprocessor 51 that forms the core of the processor 50, a timer 52 that generates timer interrupts for the microprocessor 51, a RAM 53 as an internal memory, and a data register 54 that is used for exchanging data with the DMA bus 80. Contains.

The RAM 53 is provided with a timer value storage area 55 that stores a timer value determined by the timer 52, and a trace area 56 that stores error trace information. 60 is a maintenance processor that manages system maintenance; 70
is c p u zos and input/output processor 50 , 50
... to the maintenance processor 60,
80 is [) MA Babasu. The CPU 20, the memory control unit 40, the input/output processors 50, 50, . . . , and the maintenance processor 60 are interconnected by a DMA bus 80.
Next, the operation of one embodiment of the present invention will be explained.

When system power is turned on, power-on signal 45 transitions to a low level. As a result, the counter 44 in the common timer 41 provided in the memory control unit 40 becomes ready for counting. Also, the oscillator 43 starts operating. When the output signal from the oscillator 43 is supplied to the counter 44, the counter 44 performs a count-up operation in response to the state transition of the output signal from the oscillator 43, for example, from a low level to a high level. That is, the counter 44 is
When the system power is turned on, a counting operation is performed in synchronization with the oscillation cycle of the oscillator 43. The contents of this counter 44, ie, the timer value of the common timer 41, indicate the time of the system timer. On the other hand, in the input/output processor 50,
Every time a timer interrupt is generated from the timer 52 to the microprocessor 51, the microprocessor 51 accepts the interrupt and stores the timer value storage area 5 in the RAM 53.
5 (ie, timer value) is incremented by 1. Therefore, the latest timer value (time information) is always stored in the timer value storage area 55. In addition, the microprocessor 51
The memory control unit 40
A timer read command is issued to the controller 40, and the content of the counter 44 in the control unit 40, that is, the timer value of the common timer 41, is read out from the DMA.
Read into data register 54 via bus 80. and,
The microprocessor 51 uses the RAM according to the contents of the data register 54, that is, the timer value from the common timer 41.
The timer value stored in the timer value storage area 55 in 53 is corrected. Therefore, timer value storage area 5
5, a timer value that substantially matches the timer value indicated by the common timer 41 is always stored.

Now, assume that the input/output processor 50 detects an error during data processing. In this case, the input/output processor 50
The internal microprocessor 51 issues a timer read command to the memory control unit 40 and reads the timer value of the common timer 41 into the data register 54 via the DMA bus 80. Next, the microprocessor 51 controls the data register 5.
4, that is, error trace information consisting of the timer value (error occurrence time information) from the common timer 41 and error information, is stored in the trace area 56 in the RAM 53.
Store in. The error trace information thus stored in the trace area 56 is transferred to the main memory 30 via the DMA bus 80 and the memory control section 40 in response to a command from the CPU 20, and is stored in the trace area. The CPU 20 then performs failure analysis based on the error trace information traced to the main memory 30.

The timer value in the error trace information, that is, the time information indicating the time of error occurrence, is the cycle of the system timer (501
Since it is generated by counting signals with an extremely shorter period (several tens of microseconds) than 1 second, it is much more accurate than system time. Therefore, compared to the traditional method,
Detailed time series analysis can be performed.

Next, a case where there is a failure in the DMA bus interface function or the like within the input/output processor 50 and it is impossible to transfer error trace information within the input/output processor 50 to the main memory 30 will be described. In this case, the CPU
The command from 20 will not be executed, and CP L
An error occurs at J20.

In this case, CPU 20 activates maintenance processor 60. As a result, the maintenance processor 60 issues an error trace information transfer command to the input/output processor 50. In response to a command from the maintenance processor 60, the microprocessor 51 in the input/output processor 50 stores (RAM 53
The error trace information stored in the trace area 56 (in the
Serial transfer to 0. That is, in this embodiment, if error trace information cannot be transferred to main memory 30, the same information is transferred to maintenance processor 60. Therefore, even if it cannot be traced to the main memory 30, the trace information does not disappear and failure analysis becomes possible. Note that the maintenance processor 60 may be activated manually in accordance with the lamp display accompanying the above-described error detection in the CPU 20. Furthermore, the maintenance processor 60 may be configured to periodically collect error trace information of the input/output processors 50, 50, . . . and the CPU 20.

ga1, □, i v41.7) 9i vio□, 5□:
The operation when there is no 1 will be explained. If the timer value cannot be read from the common timer 41 when an error is detected in the input/output processor 50, the microprocessor 51
The latest timer value stored in the timer value storage area 55 in the AM 53 is used instead of the timer value from the common timer 41. That is, the microprocessor 51 generates error trace information consisting of the timer value from the timer value storage area 55 and error information, and stores it in the trace area 56 in the RAM 53. The subsequent operation is similar to the case where the timer value from the common timer 41 described above is used. The timer value stored in the timer value storage area 55 substantially matches the timer value indicated by the common timer 41, as described above. Therefore, even if the timer value cannot be read from the common timer 41 when an error is detected, highly accurate failure analysis is possible.

[Effects of the Invention] As described in detail above, according to the present invention, the common timer provided in the memory control unit allows the error occurrence time to be known with high accuracy, thereby improving failure analysis accuracy. Furthermore, according to the present invention, even when time information cannot be obtained from the common timer, the time of error occurrence can be traced. Further, according to the present invention, even if error tracing to the main memory is impossible, error trace information does not disappear, so failure analysis can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a calculation line system according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 20...CPLJ, 30...Main memory, 40...
Memory control unit, 41... Common timer, 50... Input/output processor, 51... Microprocessor, 52...
...Timer, 55...Timer value storage area, 60...
・Maintenance processor, 70... Serial bus, 80...
・DMA bus.

Claims (4)

[Claims] (1) The CPU, main memory, and input/output processor are
In a computer system interconnected by an MA bus, if an error is detected during data processing in the common timer, which is provided in the memory control section of the main memory and has a higher frequency than the system timer, and the input/output processor, the above error trace information generation means for reading a timer value indicated by the common timer in the memory control unit via the DMA bus and generating error trace information consisting of the timer value and error information; and means for tracing error trace information to the main memory via the DMA bus. (2) CPU, main memory, and input/output processor are D
In a computer system interconnected by an MA bus, if an error is detected during data processing in the common timer, which is provided in the memory control section of the main memory and has a higher frequency than the system timer, and the input/output processor, the above A first timer value indicated by the common timer in the memory control unit is read out via the DMA bus to generate error trace information consisting of the first timer value and error information, and even if the first timer value cannot be read out, For example, error trace information generation means for generating error trace information consisting of a second timer value managed by the input/output processor and error information, and error trace information generated by the error trace information generation means via the DMA bus. and means for tracing to the main memory. (3) The input/output processor sets the second timer value to:
3. The error tracing method according to claim 2, wherein the error tracing method is corrected at fixed time intervals according to a first timer value indicated by the common timer in the memory control section. (4) The CPU, main memory, maintenance processor, and input/output processor are interconnected by a DMA bus, and the C
In a computer system in which a PU, a maintenance processor, and an input/output processor are interconnected by a serial bus, a common timer that is provided in the memory control section of the main memory and has a higher frequency than the system timer, and a common timer that is used to process data in the input/output processor are connected to each other by a serial bus. If an error is detected, the first timer value indicated by the common timer in the memory control unit is read out via the DMA bus to generate error trace information consisting of the first timer value and error information. error trace information generation means for generating error trace information consisting of a second timer value managed by the input/output processor and error information if the timer value cannot be read; means for tracing the error trace information generated by the error trace information to the main memory via the DMA bus, and when tracing via the DMA bus by this means is impossible, the error trace information generated by the error trace information generating means and means for transmitting data to the maintenance processor via a serial bus.