JPS6111488B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit of an AC circuit, particularly an OR circuit, and its purpose is to detect one AC input signal when a logic circuit is constructed using AC. In this case, the other AC input terminal is energized, thereby eliminating the wrap-around current between the input terminals and providing an OR circuit with a simple circuit configuration.

Generally, logic circuits are composed of DC circuits. This is due to the fact that DC circuits are easier to use for logic due to the circuit configuration, and the fact that it is easier to block current flowing between input terminals when configured with DC circuits, as shown in the above-mentioned problem. This is because the circuit is simpler when configured with a circuit. Therefore, in the logic generally used in a control device, the input information is often AC, and the load connected to the output is also AC. In this case, according to a conventionally known method, an AC input signal is first converted to DC to construct a logic circuit, and then,
The logic outputs drive relays, triacs, etc., re-energize the alternating current, and take steps to control the load.

In order to eliminate the above-mentioned drawbacks, the present invention uses PNP transistors and NPN transistors with their emitters commonly connected, and connects the collector terminals of each transistor with diodes to provide AC logic, thereby eliminating input AC signals from circulating around each other. , which provides a simple AC OR circuit. The present invention will be described in detail below with reference to the drawings.

In FIG. 1a, 1 and 2 are AC input signals connected to input terminals A and B. 3, 4, 5, 6
are diodes, which are connected so as to engage with the respective input terminals of A and B. 7 is a resistor, 8,
A diode 12 is connected in antiparallel between the base and emitter of a transistor to be described later. 1
1 is a resistor, 9 is an NPN transistor, and a low resistor 7 is connected between its base and an AC power supply 13. 10 is a PNP transistor, and a low resistor 11 is connected between its base and an AC power supply 13. 1
8 is an AC power source. Y is a logic output terminal, which is connected to a point where the emitter terminals of transistor 10 and transistor 9 are commonly connected.

FIG. 1b shows the circuit of FIG. 1a of the present invention using general logic circuit symbols, and the circuit of FIG. 1a is an OR circuit.

The operation in the above configuration will be explained. AC power supply 13, input terminals A and B signals, and output terminals〓〓〓〓
The signal relationship for Y is shown in FIG. This will be explained in comparison with FIG. FIG. 2 shows a state in which a signal is generated at input terminal A and no signal is generated at input terminal B. A signal is generated at the input terminal A from the circuit input signal 1, and a positive cycle indicated by t ₀ to t ₁ is applied to the collector of the transistor 9 through the diode 3. On the other hand, a positive voltage is applied to the base of the transistor 9 through the resistor 7.
The base current of the transistor 9 flows from the AC power supply 13 → the low resistance resistor 7 → between the base and emitter of the transistor 9 → the output terminal Y → the load (not shown) connected to the output terminal Y, and the transistor 9 is turned on. An output voltage is generated as shown from t ₀ to t ₁ of Y in Figure 3.

Next, in the negative cycle shown from t ₁ to t ₂ ,
A signal generated from the AC input signal 1 is applied to the collector of the transistor 10 through the diode 5. On the other hand, a negative voltage is applied to the base of the transistor 10 through the resistor 11, and the base current of the transistor 10 is changed from the load (not shown) connected to the output terminal Y to the emitter of the transistor 10. Base → Resistor 11 → AC power supply 1
3, the transistor 10 is turned on, and an output voltage shown from t ₁ to t ₂ of Y in FIG. 3 is generated.

Here, a feature of the present invention, which is the prohibition of alternating current signals from passing around, will be described. As described in the above operation, a signal is generated at input terminal A, but not at input terminal B. Therefore, the signal from input terminal A does not interfere with input terminal B. This operation will be described. During the positive cycle from t ₀ to t ₁ , the signal generated at the input terminal A passes through the diode 3 and the transistor 9, and a positive voltage is generated at the output terminal Y. At this time, even if the AC input signal 1 becomes higher in voltage than the AC power supply 13, the base voltage of the transistor 9 is determined by the AC power supply 13, and the transistor 9 operates as an emitter follower, so the output terminal The voltage of Y is AC power supply 13
The voltage will never be higher than the voltage of Therefore, since the base and emitter of transistor 10 are reverse biased and in an off state, the voltage generated at the emitter of transistor 9 is not generated at the collector of transistor 10. Next, even in the negative cycle from t ₁ to t ₂ , transistor 9 is turned off and transistor 10 is turned on, so that the negative voltage generated at the emitter of transistor 10 is not generated at the collector of transistor 9 . Therefore, the signal from AC signal 1 does not go around to AC signal 2 and cause interference.

As described above, according to the AC OR circuit of the present invention, there is no interference between the input AC signals due to the circulating current, and there is no need to use means of converting the input AC signals to DC, performing logic, and then converting them to AC signals again. Even with a simple configuration, it is possible to directly obtain an OR output from an AC signal.

[Brief explanation of the drawing]

Fig. 1a is an electrical wiring diagram showing an embodiment of the present invention, Fig. 1b is a circuit diagram showing the electrical wiring diagram of Fig. 1 using logical symbols, and Fig. 2 is a waveform showing the operation of Fig. 1. It is a diagram. 3, 4, 5, 6...diode, 7, 11...
Resistor, 9, 10...transistor, A, B...input terminal, Y...output terminal. 〓〓〓〓

Claims (1)

[Claims] 1 Connect the emitters of the PNP transistor and NPN transistor in common, and connect the base terminal of each transistor to an AC power supply via a resistor.
One end of a plurality of diodes corresponding to the number of logic inputs is commonly connected to each collector terminal, and the other ends of these diodes are commonly connected so as to correspond to the collector terminal sides of the PNP transistor and NPN transistor, respectively, to form a logic input terminal. and an AC OR circuit in which the emitter common connection terminal of the PNP transistor and the NPN transistor is used as an output terminal.