JPS6112059A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To produce a highly efficient memory without reducing the space of one transistor type memory cell capacitive part by a method wherein the shining direction of exposure as well as the side etching direction are fitted to the direction wherein the capacitive part is increasing. CONSTITUTION:A nitride silicon layer 32 coated on a P type silicon substrate 31 is selectively removed leaving only the active region excluding memory cell. Later the surface of substrate 31 is implanted with boron by ion implanting process utilizing the nitride silicon layer 32 as a mask to form a channel stopper impurity region as well as a thick field oxide silicon layer 33 in the oxidative atmosphere. Next the field oxide silicon layer 33 is selectively removed by photoetching process and then the exposed surface of silicon substrate 31 is implanted with arsenic or phosphorus by ion implanting process to control the threshold value voltage of transistor. The substrate 31 is coated with an oxide silicon layer 35 to be a capacitive gate insulating film by thermal oxidizing process and the layer 35 is further coated with a nitride silicon layer 36 by vapor growing process finally to form a capacitive gate electrode 37 by conventional well known process.

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides a capacitor for data storage and an M for switching.
O8) This relates to a method of manufacturing a one-transistor type memory cell consisting of one run raster.

(2) Prior Art The operating principle of transistor type memory will be explained with reference to FIG. C3 indicates a data storage capacity, and the potential of one node N corresponds to stored data. WL
is a 1 selection line and is connected to the gate electrode of the N-type transistor Q.

D is data write/read @ (hereinafter referred to as data line), and before the start of operation, the stray capacitance cd of the data line is
It has been charged to the power supply potential vCc. During writing, Q is made conductive by setting the potential of the 1 selection line WL=ii, and the capacitance and C are connected through the transistor Q and the data line.
, t-determine the potential of node N by charging or discharging. (J) - When outputting, the stray capacitance cd of the data line is charged in advance to the power supply potential V0°, and then the 1 selection line WLt is set to a high potential to make the transistor QTh conductive, and the 1 node N The potential of is the power supply potential (″′1
``data), the potential of the data line does not change (dashed line in Figure 2).When the potential of node N is the ground potential (``'O'' data).

Since the electric charge stored in the capacitor cd in advance is divided between the capacitor Cd and the capacitor C8, the potential of the data line drops by Δ■ (solid line in FIG. 2). The data line is further connected to a differential amplifier, and the above-mentioned symbol potential is amplified to complete reading. The signal difference ΔV between data "1" and "O" is.

Determined by the capacitance ratio of capacitance Cd and C5 1 Usually 40QmV ~ 6
00mV, but has a high margin against noise due to α rays and parasitic coupling capacitance.

To configure a memo IJ suitable for high-speed operation.

It is necessary to construct a memory cell with a large signal difference Δ■, that is, with a large capacitance C8.

FIG. 3 shows a mask pattern diagram of a representative example of a one-transistor type memory cell, and FIG. 4 shows a cross-sectional view taken along line xx' in FIG. 3. 11 is field i area (inactive area)
The mask 12 for determining the capacitance gate electrode, 13
is the switching transistor gate electrode. 15
18 indicates a P-type silicon substrate, 18 indicates an N+ type impurity diffusion layer serving as a source/drain region, 16 indicates a silicon nitride layer, and 14 indicates a thick silicon oxide layer serving as a field region.

The capacitance C3 is a 1 inversion layer or an N impurity diffusion layer 19
and the electrode 12, and the capacitor area is the shaded area in FIG. What should be noted here is that the shaded portion of the J4 capacitor region is smaller than the mask pattern 11 that determines the field.

This occurs due to the process of forming the entire field area. This will be explained using FIGS. 5 to 7. 2
1-line silicon substrate, 23 is a silicon oxide film, 24 is a silicon nitride film which is an oxidation-resistant film, 25 is a photoresist layer, and FIG. 5 shows a mask (
The state after the light binding phenomenon is performed using the glass 27 and the dark member 1z6) is shown in FIG. 1B (for convenience, the mask is also shown). Although FIG. 3 shows an example in which a positive type photoresist is used, a positive resist is suitable for forming a pattern with a width or spacing of 2 μm or less, and is now common. What should be noted here is that the resist pattern interval becomes wider than the mask pattern interval I11 due to the wrapping and reflection of light. Further, using the resist 25 as a mask, a silicon nitride layer 24. FIG. 6 shows the state after the silicon oxide layer 23 has been etched and removed. Next, oxidation-resistant silicon nitride layer 2
When the silicon oxide layer 2B with a thick field is formed by oxidizing the surface of the substrate 21 using 4 as a mask, the result is as shown in FIG. As shown in FIG. 7, the feature is that oxygen atoms enter from the side surfaces under the silicon nitride layer 24, creating a shape in which the silicon oxide film is embedded. It is omitted here.

As is clear from the above explanation, compared to the dimension 11 of the field determining mask, the dimension 11 after field formation is s 1 due to the wraparound of light, the wraparound of etching, the penetration of the field oxide film 28, etc. ．． Opm ~2
．． Wider by 0μm.

on the other hand! , the resolution of the resist and exposure machine is the limit, and the resolution is 0.
A value of about 8 μm to 2.0 μm is common.

For example, the memory cell shown in Figure 3 (cell size 811m
11 μm), the area of the capacitive part on the mask is approximately 46 μm2 after one dimension change (indicated by the broken line)
is approximately -2 μm2, which is a decrease of more than 501. the result.

The signal amount during readout is reduced, resulting in a decrease in yield due to insufficient noise margin or an obstacle to high-speed operation.

(3) Purpose of the Invention An object of the present invention is to provide a manufacturing method that can realize a high-performance memory without reducing the area of the capacitive portion of a one-transistor type memory cell.

(4) Structure of the invention' The present invention relates to a method for manufacturing a one-transistor memory.
A step of selectively depositing a film containing at least an oxidation-resistant material layer on a region other than a memory cell on one main surface of a semiconductor substrate that is to become an active region, and using the film as a mask on the semiconductor substrate.

a step of forming a thick silicon oxide film; a step of selectively removing the thick silicon oxide film in a region where a memory cell is to be formed to expose the semiconductor substrate surface; and forming a capacitor gate insulating film on the exposed substrate surface. A method of manufacturing a semiconductor memory is characterized in that it includes a step of forming a capacitor gate electrode, and a step of selectively forming a capacitor gate electrode.

(5) Examples Examples will be explained using FIGS. 8 to 11. 1
After oxidizing a P-type silicon substrate of about 00 cm in an oxidizing atmosphere and depositing a silicon oxide layer of about 600 cm, s' 2
A silicon nitride layer 32 of approximately 0.000000 layers is deposited by vapor phase growth. The silicon nitride layer 32 is selectively removed by a well-known etching and etching method, leaving only active regions other than memory cells. Thereafter, using the silicon nitride layer 32 as a mask, for example, boron is introduced into the substrate surface by ion implantation to form a channel strike and a spring blunt region, and then a thick field silicon oxide layer is formed in an oxidizing atmosphere. 33e About 8,000 layers are formed (Fig. 8).

The entire field silicon oxide layer in the memory cell formation area is selectively removed using a known photoetching method, and then arsenic or phosphorus is introduced into the exposed silicon substrate surface using an ion implantation method to improve the transistor threshold. Fully control the value voltage. In FIG. 9, numeral 34 indicates a photoresist. The silicon oxide layer 35, which is to become a capacitor gate insulating film, is deposited by gold thermal oxidation method, and the silicon nitride layer 36t is deposited by vapor phase growth method, each having a thickness of 100 A and 300 layers, respectively. Next, as shown in FIG. 10, about 6,000 polycrystalline silicon layers are grown by full vapor phase epitaxy, and phosphorus is further diffused at 1,000° C. to lower the resistance of one layer. A capacitor gate electrode 37t is formed using a known photoetching method. The capacitor gate electrode is oxidized in an oxidizing atmosphere.
Approximately 5,000 layers of interlayer insulating film 38 are formed. At this time, since the silicon nitride layer 36 is oxidation resistant, other regions are hardly oxidized.

After that, a silicon nitride layer 36°, a silicon oxide layer 35,
Moreover, the silicon nitride layer 32. The silicon oxide layer is removed and the silicon substrate 31t in the active region is exposed. Gate silicon oxide 2 layer 40t'7 in oxidizing atmosphere
After forming 00A.

Deposition of polycrystalline silicon layer t'6000A by vapor phase growth,
Phosphorus is introduced, one-layer resistive metal processing is performed, and a gate electrode 39t is formed by photo-etching. Using the gate electrode 39 as a mask, arsenic is introduced into the substrate surface in a self-aligned manner by ion implantation to form a north drain diffusion layer region 41 (gold).
Figure 11).

Then, after depositing PSGt-1.0 μm by vapor phase epitaxy and forming contact openings by photoetching, aluminum wiring is formed by subbing and taring, and a PSG passivation film is formed by vapor phase epitaxy. Semiconductor memory is completed.

(6) Effects of the Invention As shown in FIG. 9, according to the present invention, there is no penetration of the field oxide film into the memory cell capacitance portion, and the aforementioned reduction in the area of the capacitance portion is eliminated. The area twice as large becomes the capacitive part.

In addition, the direction of light wrapping during exposure and the direction of side etching during etching are different from conventional technology.

The trend is to increase the capacitance, and moreover, it is not limited by the resolution limit of the resist/exposure machine.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams for explaining the operating principle of a one-transistor type memory. FIG. 3 is a mask pattern diagram of a typical l-transistor type memory cell, and FIG. 4 is a cross-sectional view taken along line xx' in FIG. Figures 5 to 7
The figure is a cross-sectional view for explaining a conventional technique for forming a field region. FIGS. 8 to 11 are cross-sectional views of an embodiment of the present invention. In FIG. 1, numerals 11, 12, and 13 indicate mask patterns for determining the field, capacitor gate electrode, and gate electrode, respectively. 15, 21.31 is a P+ type silicon substrate, 23 is a silicon oxide film, 24.32 is a silicon nitride film, 25.34 is a resist, 14, 28.33 is a field silicon oxide layer, 16.36 is a capacitor gate insulation Silicon nitride layer forming the film, 12.37 is capacitor gate electrode + 13.39 is gate electrode, 18.41 is N impurity diffusion layer, 17.38 is interlayer silicon oxide layer, 35 is silicon oxide of capacitor gate insulating film The layers 40 are the gate silicon oxide layer, 26 and 27 are the dark material and glass plate forming the photomask, respectively. #2 Fig. 3 UA East 4 Fig. - Grass, fI! I Arithmetic 6 Illustration 7

Claims (1)

[Claims] A step of selectively depositing a film containing at least an oxidation-resistant material layer on a main surface of a semiconductor substrate in a region other than a memory cell that is to become an active region, and using the film as a mask, depositing a thick oxide layer on the semiconductor substrate. a step of forming a silicon film; a step of selectively removing the thick silicon oxide film in a region where a memory cell is to be formed to expose the surface of the semiconductor substrate; and a step of forming a capacitor gate insulating film in the region. and selectively forming a capacitor gate electrode.