JPS61128309A - Reset control circuit - Google Patents

Abstract

PURPOSE:To set up the lower limit power supply voltage of operation with a simple constitution by forming a reset terminal validated only at the use of a high speed clock by the control of a clock switching signal and a reset terminal validated independently of a clock used. CONSTITUTION:A clock switching control part 4 generates a switching signal C for switching a high speed clock and a slow clock. The signal C is turned to 'L' at the use of the high speed clock, and turned to 'H' at the use of slow clock. When a reset terminal B2 is turned to 'L' at the use of the high speed clock, the output of a NOR gate 5 is turned to 'H' and the output of a NOR gate 6 is turned to 'L'. A processor is reset by a reset sequence generating part 7. When a reset terminal A1 is turned to 'L', the output of a NOT gate 3 is turned to 'H' and the output of the gate 6 is turned to 'L', so that the processor is reset independently of the clock used. In this case, 3.5V and 4.5V detecting circuits 8, 9 output 'H' signals if the voltage is a prescribed one or more, and output 'L' signals if less than the prescribed voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reset control circuit for a microprocessor that switches between two systems of oscillation clocks.

BACKGROUND OF THE INVENTION In a conventional microprocessor, a reset is applied before the power supply voltage becomes a constant voltage to prevent the program progression from malfunctioning when the power supply voltage becomes smaller than the constant voltage. For this purpose, a constant voltage detection circuit is connected to the reset terminal to set the operating lower limit voltage (for example, Japanese Patent Laid-Open No. 66-53717).

On the other hand, conventional microprocessors are equipped with a switching device between a high-speed clock and a low-speed clock. For example, during standby, the high-speed clock used in normal use is switched to a low-speed clock to reduce power consumption. During normal use, processing is performed by switching back to the previous high-speed clock (for example, Japanese Patent Laid-Open No. 59-5328).

Problems to be Solved by the Invention Even in a processor that switches between two systems of clocks, such as the conventional example above, there is only one reset terminal, and only one lower limit operating voltage value can be set. Met.

In such a configuration, even if the lower operating limit voltage that can be tolerated when using a high-speed clock is different from the lower operating limit voltage that can be tolerated when using a low-speed clock; , the problem is that only the minimum operating voltage that is allowable with high-speed clocks can be set.

In view of the above, it is an object of the present invention to provide a reset control device that has a simple configuration and can set the lower limit power supply voltage for high-speed clock operation and the lower limit power supply voltage for low-speed clock operation.

Means for Solving the Problems The present invention provides a clock switching device that outputs a clock switching signal indicating the use status of a high-speed clock and a low-speed clock, and a first clock switching device that is effective only when the high-speed clock is used by controlling the clock switching signal. and a second reset terminal that is valid regardless of the clock used,
The reset control device is characterized in that a lower limit voltage detection circuit for high-speed operation is connected to the reset terminal of the second reset terminal, and a lower limit voltage detection circuit for low-speed operation is connected to the second reset terminal.

Effects The present invention has the above-described configuration, so that if the lower limit voltage for high-speed operation is higher than the lower limit voltage for low-speed operation, when the power supply voltage is lower than the lower limit voltage for high-speed operation and a high-speed clock is used, high-speed operation is possible. The lower limit voltage detection circuit applies a reset signal to the first reset terminal to reset the processor, but when a low-speed clock is used, the first reset terminal is disabled under the control of the clock switching signal and the processor is reset. Not reset. Furthermore, when the low-speed clock is used, when the power supply voltage becomes lower than the lower limit voltage for low-speed operation, the lower-limit operation voltage detection circuit for low-speed operation applies a reset signal to the second reset terminal, and the processor is reset.

Embodiment FIG. 1 shows a block diagram of an embodiment of a reset control circuit for a microprocessor according to the present invention.

In FIG. 1, 1 is a reset terminal A, 2 is a reset terminal B, 3 is a NOT gate that inverts the output of the reset terminal A1, and 4 is a high-speed clock or low-speed clock switching signal C.
5 is a NOR gate that receives the input signal of the reset terminal B2 and the output C of the clock switching control section 4, and 6 is a clock switching control section that outputs the output of the NOT gate 3 and the NOR gate. NO with the output of 5 as input
R gate, '7 is a reset sequence generator which takes the output of the NOR gate 6 as a reset input and generates a processor reset sequence when the input d is 1L''; 8 is 3;
．． This is a 5V detection circuit, and its output is connected to the reset terminal A above.
1, and 9 is a 4.6V detection circuit whose output is connected to the reset terminal B2.

The power supply voltage is usually 6. It shall be used in Ov.

The reset clock switching control section 4 of this embodiment configured as described above generates a switching signal C between a high speed clock and a low speed clock. When used, it becomes i@H'. Therefore, when using a high-speed clock, that is, when the clock switching signal is I, when the reset terminal B2 becomes L, N
Since the output of the OR gate 6 becomes ``H'' and therefore the output of the NOR gate 6 becomes @L1, the processor is reset by the reset sequence generator 7. However,
When a low-speed clock is used, the clock switching signal C becomes 1H", so even if the reset terminal B2 becomes @L", the processor is not reset.

On the other hand, when the reset terminal A1 becomes @L'', the output of the NOT gate 3 becomes 'H', and therefore the output of the NOR gate 6 becomes g I,+e, so that the processor is reset regardless of the clock used.

The 3.6v detection circuit 8 outputs @L'' when the power supply voltage is smaller than 3.5V, and outputs @H'' when the power supply voltage is 3.5V or more. Further, the 4.6v detection circuit 9 has a power supply voltage of 4.5V.
When it is smaller than v, it outputs @L", and when it is 4.6v or more, it outputs '"H".

It is assumed that when the processor is reset, a high-speed clock is selected as the clock.

FIG. 2 shows a timing chart for changes in power supply voltage when a high-speed clock is used.

In the figure, a shows the state of the reset terminal A1, b shows the state of the reset terminal B, C shows the clock switching signal output from the clock switching control section 4, and d shows the state of the input to the reset sequence generating section 7.

When the power supply voltage is less than 4.5■, reset terminal B
2 input is w 1. a, and when a high-speed clock is used, the clock switching signal C is IILII, so the processor is reset, and when the power supply voltage becomes 4.5 V or higher, the reset is canceled and high-speed operation is performed.

That is, during high-speed clock oscillation, it is reset when the power supply voltage becomes smaller than 4.5V.

FIG. 3 shows a timing chart for changes in power supply voltage when switching to a low-speed clock.

The signal names in the figure are the same as in FIG. 2.

During a power-on reset, the high speed clock is selected, so when the power supply voltage is less than 4.6cm, the processor is in a reset sequence.

When the power supply voltage becomes 4.5V or higher, a reset signal a is generated.

Since both B and B become @H'', operation is performed using the high-speed clock.Next, when the clock is switched by a command and a low-speed clock is used, the clock switching signal C becomes wHB, and the state of the reset terminal B2 is invalid regarding the set. Therefore, at this time, the reset is performed depending on the state of the reset terminal A1.

In other words, when using a low-speed clock, the power supply voltage is 3
．． A reset is performed when the value becomes smaller than 5■.

As described above, according to this embodiment, the clock switching signal is
A reset terminal B2, which is valid only when the high-speed clock is in use, and a reset terminal A1, which is valid regardless of the clock used, are provided.A 4.5V detection circuit is connected to the reset terminal B2, and the reset terminal B2 is valid only when the high-speed clock is in use. A1 has 3.
By connecting a 5V detection circuit, when a high-speed clock is used, it is reset when the power supply voltage becomes less than 4.6V, and when a power supply abnormality occurs during high-speed operation, it is reliably reset, and when a low-speed clock is used, that is, power saving operation. When the power supply voltage becomes smaller than 3.6V, a reset can be applied to provide a margin against power supply fluctuations during low-speed operation.

In addition, in this example, the lower limit voltage for operation when the system clock is set to a high speed clock is 4.5V, and the lower limit voltage for operation when set to a low speed clock is set to 3.5V, but these voltages are limited to these values. It is not a fixed value, but should be set to a value that corresponds to the system situation.

Effects of the Invention As described above, according to the present invention, the lower limit power supply voltage when using a high-speed clock and the lower limit power supply voltage when using a low-speed clock can be set with an extremely simple circuit configuration. The practical effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a reset control device according to an embodiment of the present invention, FIG. 2 is an operational waveform diagram for changes in power supply voltage when using a high-speed clock of the same embodiment, and FIG. 3 is a high-speed clock of the same embodiment. FIG. 4 is an operation waveform diagram for changes in power supply voltage when switching from a low-speed clock to a low-speed clock. 1... To reset terminal, 2... Reset terminal B, 4... Clock switching control unit/Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Vcc Figure 3 %t

Claims (1)

[Claims] A clock switching circuit that outputs a clock switching signal indicating the use status of the high-speed clock and the low-speed clock, a first reset terminal that is enabled only when the high-speed clock is used under the control of the clock switching signal, and a first reset terminal that is enabled regardless of the clock used. What is claimed is: 1. A reset control circuit comprising: a second reset terminal;