JPS61128352A - Data transfer system - Google Patents

Abstract

PURPOSE:To reduce the number of driver circuits in an I/O device by forming plural channels for counting up addresses in a memory and outputting a channel specifying signal at the transfer of data. CONSTITUTION:A CPU sets up a leading address in a counter having a presetting function and then sets up a channel No. of a memory to be used in a channel register of a register part 41' of an I/O control device 4. Obtaining a bus using right, the control part 41' outputs a channel address signal and a control signal. The memory discriminates these signals, validates an address gate signal corresponding to the channel concerned and reads out and outputs the data to a bus 3. The control part 41' enters the data on the bus 3 into a register part 42', transfers the data to an I/O device 5 and counts down the number of transfer words in a command register of the register part 42' by '-1'. A series of operation is executed until the number of transfer words in the command register is turned to zero.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a common path data transfer method in which a plurality of information processing units are connected via a common data bus, and <1=memory capacity. Demand for increased data transfer speed and increased demand for data transfer speed C: This relates to the common bus data transfer method that has been addressed.

[Conventional technology]

FIG. 3 shows the configuration of this type of common path type information processing apparatus. In Figure 3, 1-1 to 1-i are CPUs, 2-1 to 2-
j is a main storage device (hereinafter referred to as memory); 3 is a common bus;
4-1 to 4-h are input/output control devices (PL, lower roc
It is written as ), 5-1 to 5-h are input/output devices (hereinafter 110
It is written as equipment. ), 6 is a 7-end control device, and 7 is a Fytum device.

FIG. 4 is a functional block diagram of l0C4-1 to 4-h. In addition, the following explanation is simplified to C; in order to proceed, the CPU,
The IOC, 110 equipment, and memory are collectively referred to as -r,
cPU1, l0Ca, 110 equipment 5, iMo! j
I will explain it in two steps. In FIG. 4, 41 is a control section, and 42 is a register section such as a command register, a status register, a data buffer register, and an admit register.

3 and 4 (from 2), we will explain the operation of outputting IOC47JI ILO data in accordance with the command of cpv 1.CPVL senses the status register of the register section 42 of the concerned I0C4 and determines whether it is in operation or not. After confirming that, address register C
Set the start address of command register l.
2 transfer word count and transfer direction, in this example memory 2 to I10
At the same time as indicating the direction of the device 5, the control section 41'&quot;

As shown in the data transfer operation time chart of FIG.
:'& get the right to use the path, address signals and control signals? Common bus 5 C output and read data from memory 2, read data? A data transfer operation to initialize the data buffer register 1 of the register section 42 is executed.

Next, the data f in the data buffer register is transferred to the I10 device 5, and a transfer completion signal is received from the I10 device 5. After this, the value of the address register of the register section 42 is increased by +1.
Executes the operation of increasing the number of transferred words in the command register by +1,
One data transfer operation is completed, but this series of data transfer operations is executed until the number of transfer words in the command register of the register section 42 becomes "zero".

[Problem that the invention seeks to solve]

As mentioned above, in the common path method, there is a strong demand for increased memory capacity and faster data transfer speed. Looking at the impact of increased memory capacity on l0C4, the address signal to common path 3 is transferred to memory 2. Since it is necessary for the entire area of
What used to be 16 to 20 bits has increased to 24 to 32 bits. As a result, the conventional (
In comparison, a large number of integrated circuits (hereinafter referred to as ICs) are required.

On the other hand, looking at the impact of increasing data transfer speed on 10C4, we can see that conventional driver elements such as RC 5N7
458 (manufactured by Tekinasu Instruments Inc. (Ti), which used a driver element, but the 5
C2 is now using N7485B (manufactured by Ti, high-speed driver IC). As a result, there is a problem in that the current consumption of the driver element has significantly increased. i.e. SN 7438 x 20 bits to 5N74S
The increase in current consumption for 58 x 52 bits is 150mA =
B'mAX52 (bits) - 5mAx20 (bits), and considering the data signal, the total increase is 500mA, considering that the current consumption of the card equipped with Iclso is about 2 to 5A. and very (two big increases).

Problems related to the above two problems When looking at all the devices as a whole, the problem is becoming even bigger because the processing capacity of the CPU 1 is increasing (and the number of IOCs 4 is also increasing).

[Means for Solving the Problems J] In order to solve the above-mentioned problems, the present invention provides information on a common path system in which at least a computer, a main storage device, and an input/output control device are connected to a common path. The main memory of the processing device (main memory), the address signal of the bus (2), and the means to be addressed from the computer or input/output control device!!!, and the increment of the address Function, Dina 6
If the address is incremented and/or the address is added to the channel, it is called the channel. The input/output control device l2 is equipped with an access means to the channel nine, and the input/output control device l2 is
The IOC has a means for specifying a channel of the main storage device, and the input/output control device operates the means for specifying the channel of the main storage device during data transfer with the main storage device. As a characteristic.

[・effect]

The present invention is based on the fact that the ROC data transfer operation is a block transfer, and uses the at, reply increment and/or decrement functions called channels due to the influence of the high integration of semiconductor memory 9f blocks (-). The number of memory units is decreasing, and when data is transferred, a channel designation signal is sent from the IOC instead of an address signal (normally 16 channels are sufficient).

) The address signal to the memory element must be supplied from a channel within the same unit. The configuration of the IOC is small in number and consumes less current (2), which enables high-speed data transfer operation.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the configuration of an l0C4 according to the present invention. The same reference numerals as in FIG. 4 indicate the same parts.

In FIG. 4, 41' is a control section, and 42' is a register section.

The difference from the configuration of the conventional example shown in FIG.
The channel register g;

Figure s2 is a block diagram of an embodiment of the configuration of the memory 2 according to the present invention. In Figure 2, 21-0 to 21 to 15 are counters with presets, and 22-0 to 22-16 are memo 9t.
fB Address selection gate to 24, 25 is a renaper,
25 is a data output gate to the common path, and 26 is a control section.

From FIG. 1 and FIG. 2, the operation of this embodiment will be explained using an example in which the previously explained l0C4 outputs data from the I10 device 5. CPσ1 senses the status register of the l0C4 concerned. , after confirming that it is not in operation, the corresponding preset counter 21CCHWTH in memory 2
The start address of the memo 92 is set by manipulating the signal (f channel write signal) -1CHAO to 5 (channel address signal) and data signal. At this time, the control unit 26 of the memory 2 outputs the first address signal LA;S at a predetermined timing.
Writing the data to the preset counter 21 as one valid value from O to 15 (; becomes. Next, cpv
i is the channel register of the register unit 42' of the relevant IQC4 (;, the channel code of the memory to be used is set to t, and C; In the embodiment, from memory 2 to Ilo
At the same time as instructing the direction of the device 5, the control section 41' is activated.

As shown in the time chart (2) of the data transfer operation for the fifth cause, the control unit 41' first executes the path usage right acquisition operation.Once the path usage right is acquired.

Channel address signal (CHA
O~5) and control signals are output from the common path 5c2, and Q waits for data to be read from memory 2.
O~3), control signals (in this embodiment, a signal indicating that a channel is selected (cH multiplication signal is "1"), a signal instructing to read data from the memory 2 (RD
The control unit 26 reads the double signal "double", and at a predetermined timing C2, an address gate signal (any one of the AGo to 15 signals) corresponding to the channel C2,
The memory read signal (EDM) and the data output gate signal (RDG) to the common bus 5 are enabled to execute a data read operation. Then, an ACK signal indicating that valid data has been output from the common bus 5 (common path 5C)
2 outputs and transmits l0C41''.

10C4 (7) Control a n 41' C, ACK signal w
Mite, common bus 5. The above data is transferred to the data buffer register of the register section 42' (2 take in, then the C2 common bus 5
Channel address signal CHA O~6 outputted above
and turn off the control signal. Next, the data in the data buffer register of the register section 42' is converted to 1/Q B field C
,HeIG Yo+1 //) ―”E W a,C
-r Receives the optical 67 signal, executes an operation of decrementing the number of transfer words in the command register of the register section 42' by 1, and completes one data transfer operation. This -4 consecutive data transfer operation is executed until the number of transfer words in the command register of the register section 42' reaches "0"C;. - The contents of the counter 21 of the selected channel of the memory 2 are determined based on the timing at which the read operation of the memory 2 ends, that is, the successive output signal HAD of the control signal of the common bus 5.
+1 signal S is sent from the control unit 26 at the timing when
i (!-0 to 15' in this embodiment) is output and the content is incremented by +1. From this (2), when the next continuous output command C is executed, the memory address becomes the previous address (21).

The above has been an explanation of the operation of reading data from the memory 2 and outputting it to the I10 device 5, but the operation of reading data from the Ilo @ device 5 and writing it to the memory 2 (also regarding the second
The data transfer direction is reversed (the transfer operation of the control unit 41' of 10C4, the transfer operation of the control unit 41' of the 10C4, and the water filling of the memory 2 when the data transfer direction is reversed). This indicates that the operation can also be performed by direct instruction of the address signal from the common path 5. At this time, if the channel selection signal (CH3) is set to "0" and read/write to the memory 2 is executed. common path 3
address signal! dress selection game) 22-16'
The memory section 24 is directly led through L'.

In the above embodiment, the address increment of the channel of Mesosu 2 is +1, that is, addition, but this can be changed to -1 if the subtraction power wanta is used, or -1 if the renumber kakunta is used. It is also possible to specify C2 addition or subtraction for each channel. In Figure 2, CHWT is a channel write signal, and WT
is the memory 1 write signal, CH8 is the channel selection signal,
SO~15 is a step signal, and WTM is a memory write signal.

〔Effect of the invention〕

As described in detail above (;, the present invention ζ), a plurality of channels are provided for incrementing (adding or subtracting) the I-fiC near address of the memory 2, and the middle ini of the roc4 is the address register of the register section. Instead, a channel register for C two-channel instruction is provided, and during data transfer, a two-channel instruction signal is output instead of an address signal, which has the effect of drastically reducing the number of driver circuits for 10C4. For example, the number of address signal lines is 32 +
4 (address parity), and if the number of channel instruction signal lines is 4 + 1 (parity), the reduction will be 51 (approximately 8 in terms of the number of ICs), and the current consumption will be 52C; , calculated using a high-speed operation element such as 5N74858, the reduction is approximately 250, which is a field A (31 8-door AX).

This has a very large effect when viewed from the perspective of the entire device. In other words, the number of l0C4 used is as large as 8 to 16, so
For the entire device, the number of ICs is reduced by 64 to 128, and the current consumption is reduced by 2 to 4 A. If the above calculation is expressed as a percentage, the reduction will be 5 to 10% in - example.

In addition, in the memory 2 (the second is the preset kakunta 2l-a (%! 0 to 15 in the embodiment) that configures the channel and the address selection game) 22-11 (in the embodiment, the screen 2l-a)
~16) is required, which means r
What was in OC 4 has been moved to memory 2 (), so the increase in the number of ICs is slight, and due to advances in semiconductor technology (higher integration is achieved by memory).
Since it is most effective against the two problems, it has the advantage of being easy to implement and design.

Also, when the data transfer rate is low, the signals on the common path 5 are only output as address signals and channel designation signals instead.

Since the data transfer operation is exactly the same, high-speed transfer operation is ensured as in the prior art.

[Brief explanation of drawings]

Figure s1 is a configuration block diagram of an embodiment of the human output control device (IOC) of the present invention, Figure 2 is a configuration block diagram of the main storage device (memory) of the present invention, and Figure 's3 is information on a normal common path configuration. FIG. 5 is a block diagram of a configuration of a processing device, FIG. 4 is a block diagram of an example of a conventional human output control device (IOC), and FIG. 5 is a time chart of a data transfer operation. 1-1 to l-i.-CPU, 2-1 to 2-j...Memory, 541...Control unit, 42...Register unit, 41
'...Control unit, 42'...Register unit, 21-0~
21-15- Kawanta with preset, 22-0~2
2-16...Address selection gate. 23... Receiver, 24... Memory section, 25...
Data output gate, 26... Control unit Patent applicant Fuji Facom Control Co., Ltd. Agent Patent attorney Gobe Tamamushi (2 others) Figure 1 Figure 5 Operation Figure 2 IIl

Claims (1)

[Claims] In an information processing device configured by connecting at least a computer, a main storage device, and an input/output control device to a common bus, the main storage device includes a means that is addressed by an address signal of the common bus and a device in the main storage device. means for setting an initial value from the computer or input/output control device and being addressed from a channel provided with an address increment function, the input/output control device controlling the channel of the main storage device 1. A data transfer method, comprising: means for specifying a channel of the main memory device, wherein the input/output control device operates the means for specifying a channel of the main memory device when transferring data with the main memory device.