JPS61129355U - - Google Patents
Info
- Publication number
- JPS61129355U JPS61129355U JP1407185U JP1407185U JPS61129355U JP S61129355 U JPS61129355 U JP S61129355U JP 1407185 U JP1407185 U JP 1407185U JP 1407185 U JP1407185 U JP 1407185U JP S61129355 U JPS61129355 U JP S61129355U
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- insulating layer
- base
- connecting conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の実施例に係わるマルチエミツ
タトランジスタの半導体基体表面を示す平面図、
第２図はリード線及び配線導体を除いてトランジ
スタチツプの表面を示す平面図、第３図はリード
線を除いてトランジスタチツプの表面を示す平面
図、第４図は完成したトランジスタの第３図の
―線に相当する部分を示す断面図、第５図は完
成したトランジスタの第３図の―線に相当す
る部分を示す断面図、第６図は完成したトランジ
スタの等価回路図、第７図は第３図の―線の
一部を示す断面図、第８図は第３図の―線の
一部を示す断面図、第９図は従来のマルチエミツ
タトランジスタを示す平面図である。
１１…シリコン基体、１２…コレクタ領域、１
３…ベース領域、１３ａ…ベースリード接続領域
、１４，１４ａ…エミツタ領域、１５…Ｐ型領域
、１６…抵抗用Ｐ型領域、１７…絶縁層、１８，
１９，２０，２０ａ，２０ｂ，２１…開口、２２
…ベース接続導体層、２３…エミツタ接続導体層
、２６…エミツタリード線、２７…ベースリード
線。
FIG. 1 is a plan view showing the surface of a semiconductor substrate of a multi-emitter transistor according to an embodiment of the present invention;
Figure 2 is a plan view showing the surface of the transistor chip excluding lead wires and wiring conductors, Figure 3 is a plan view showing the surface of the transistor chip excluding lead wires, and Figure 4 is a third view of the completed transistor. Figure 5 is a cross-sectional view of the completed transistor corresponding to the line - in Figure 3, Figure 6 is an equivalent circuit diagram of the completed transistor, Figure 7 is a sectional view showing a part of the line - - in FIG. 3, FIG. 8 is a sectional view showing a part of the line - - of FIG. 3, and FIG. 9 is a plan view showing a conventional multi-emitter transistor. 11...Silicon base, 12...Collector region, 1
3... Base region, 13a... Base lead connection region, 14, 14a... Emitter region, 15... P-type region, 16... P-type region for resistance, 17... Insulating layer, 18,
19, 20, 20a, 20b, 21...opening, 22
...Base connection conductor layer, 23...Emitter connection conductor layer, 26...Emitter lead wire, 27...Base lead wire.
Claims (1)
、 前記ベース領域内に島状に設けられた複数のエ
ミツタ領域と、 前記複数のエミツタ領域の中の少なくとも１つ
の上に設けられた絶縁層と、 前記１つのエミツタ領域の上を横切るように前
記絶縁層上に設けられたベース接続導体層と、 前記ベース接続導体層の一方及び他方の側にお
いて前記１つのエミツタ領域に達するように前記
絶縁層に形成された一方及び他方の開口と、 前記一方及び他方の開口を通して前記１つのエ
ミツタ領域に接続された一方及び他方のエミツタ
接続導体層と を有するマルチエミツタトランジスタ。[Claims for Utility Model Registration] A collector region, a base region provided on the collector region, a plurality of emitter regions provided in an island shape within the base region, and at least one of the plurality of emitter regions. an insulating layer provided on the one emitter region; a base connecting conductor layer provided on the insulating layer so as to cross over the one emitter region; and a base connecting conductor layer provided on the insulating layer so as to cross over the one emitter region; A multi-emitter device having one and the other openings formed in the insulating layer so as to reach one emitter region, and one and the other emitter connecting conductor layers connected to the one emitter region through the one and other openings. Ivy transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985014071U JPH0442917Y2 (en) | 1985-02-01 | 1985-02-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985014071U JPH0442917Y2 (en) | 1985-02-01 | 1985-02-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61129355U true JPS61129355U (en) | 1986-08-13 |
| JPH0442917Y2 JPH0442917Y2 (en) | 1992-10-12 |
Family
ID=30498658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985014071U Expired JPH0442917Y2 (en) | 1985-02-01 | 1985-02-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442917Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115857A (en) * | 1981-12-28 | 1983-07-09 | Mitsubishi Electric Corp | Semiconductor device |
-
1985
- 1985-02-01 JP JP1985014071U patent/JPH0442917Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115857A (en) * | 1981-12-28 | 1983-07-09 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442917Y2 (en) | 1992-10-12 |
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