JPS61129860A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To produce with simple process the title device increased in integration with the reduction in area of the region of a high resistant element, by a method wherein a high resistant element connected to a low resistant layer via metallic layer is provided, the top of which layer is connected to a low resistant wiring. CONSTITUTION:A groove 22 is formed in the main surface of a P type Si substrate 21 and thermally oxidized, thus forming a thermal oxide film 23 on the surface of the substrate 21 including the inside of the groove 22. Successively, polycrystalline Si is deposited over the whole surface along the groove 22 and then formed into a low resistant polycrystalline Si layer 24 by diffusion of e.g. phosphorus and patterning. A groove 25 corresponding to the groove 22 is formed inside this Si layer 24. Mo 26 is evaporated over the whole surface including the groove 25, and a photo resist 27 is formed over the whole surface; then, Mo is left only at the bottom of the groove 25 by etching. Thereafter, a thermal oxide film 28 is formed over the surface of the Si layer 24 by heat treatment. A high resistant polycrystalline Si layer 29 is deposited in the groove 25, and As ions are implanted to its surface. Next, a high resistant element 30 is embedded in the groove 25 and connected to the Si layer 24 via Mo layer. A connection hole 32 is bored and an Al electrode 33 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly used for a semiconductor device having a high resistance element.

(Technical Background of the Invention and Problems thereof) In recent years, polycrystalline silicon with a selectively reduced amount of impurities has been widely used as high-resistance elements due to the demand for miniaturization of elements in general for ultra-LSIs.

The end regions of a high resistance element of such a semiconductor device, for example a static RAM, are shown in Figures M3 and 114.

In FIG. 3, for example, an insulating film 2 is formed on a P-type silicon substrate 1, and a high resistance element 3 made of a polycrystalline silicon film is formed on this insulating film 2. Further, a glabellar insulating film 4 is deposited over the entire surface of the high resistance element 3, and contact holes 5.5 are formed at both ends of the high resistance element 4.

Further, the contact hole 5.5 is formed on the glabella insulating film 4.
An Aj2 wiring 6.6 is formed which is connected to the high resistance element 3 via.

Further, in FIG. 4, for example, an N0 type diffusion layer wiring 12 is formed on the main surface of a P type silicon substrate 11, an insulating film 13 is deposited on the entire surface of the substrate 11, and the N''! diffusion layer wiring 12 is formed on the main surface of a P type silicon substrate 11. A contact hole 14 is formed at the upper position.The contact hole 14 is formed on the insulation film 13.
A high resistance element 15 made of polycrystalline silicon is formed, one end of which is connected to the N" type diffusion layer wiring 12 via a .

Furthermore, interlayer insulation 1116 is deposited on the entire surface, and a contact hole 17 is opened at the other end side of the high-resistance element 15 . Furthermore, an AJ2 wiring 18 connected to the high resistance element 15 via a contact hole 17 is formed on the interlayer insulation layer 1i11116.

In the conventional semiconductor KM shown in FIGS. 3 and 4,
In order to take electrodes from both ends of the high resistance element 3 or 15 made of polycrystalline silicon, the high resistance element 3 or 15 and other low resistance wiring (the β wiring 6 or 18 or the N" type diffusion layer wiring 12) are connected. A certain amount of area is required in consideration of the area of the contact hole 5.14 or 17 for connection and the allowance for alignment thereof, that is, allowance for pattern formation by photolithography.

For example, when forming a high-resistance element on the order of gigaohms (10sΩ), three layers of polycrystalline silicon are required as an effective high-resistance region other than the high concentration area for making ohmic contact, and one layer of polycrystalline silicon is required. The alignment margin for the contact hole and its surroundings is 1 m, that is, two contacts are required for the contact part, and four electrodes are required for the electrodes at both ends. In other words, a length of 7 tm is required for the high-resistance element, the contact hole, and the margin thereof, which is a major obstacle in achieving high integration of, for example, a large-capacity static memory.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a highly integrated semiconductor device that requires less area for an effective high-resistance element, and a method for easily manufacturing such a semiconductor device. This is what we are trying to provide.

[Summary of the invention]

A semiconductor device according to a first aspect of the present invention includes a low resistance layer (a conductor layer or a diffusion layer) formed on a main surface of a semiconductor substrate and having a groove inside, and a low resistance layer formed on at least the low resistance layer at the bottom of the groove. a metal layer, a high resistance element buried in the groove via an insulating film formed on the surface of the low resistance layer at least on the side wall of the groove, and connected to the low resistance layer via the metal layer; The device is characterized in that it includes a low resistance wiring connected to the top surface of the device.

According to such a semiconductor device, since the high resistance element is formed in the groove in the depth direction of the substrate, the area required for the effective high resistance element extends to the contact hole with the low resistance wiring above it. This overlaps with the area required for the alignment margin, and the planar area of the high resistance element region can be significantly reduced.

Further, the method for manufacturing a semiconductor device according to the invention of Part 2 of the present application includes a step of forming a low resistance layer having an inner groove on the main surface of the semiconductor substrate, and selectively forming a metal layer on the low resistance layer at least at the bottom of the groove. a step of performing thermal oxidation to form an oxide film on at least the surface of the low-resistance layer on the trench sidewall; a step of embedding a high-resistance element in the trench; and a step of burying an impurity in the surface region of the high-resistance element. and a step of forming a contact hole after forming an interlayer insulating film on the entire surface and forming a low-resistance wiring connected to the upper surface of the high-resistance element. It is.

According to such a method, the semiconductor device of the invention of the present invention can be manufactured by an extremely simple method.

[Embodiments of the invention]

Examples of the present invention will be described below along with the manufacturing method shown in FIGS. 1(a) to 1(f).

First, for example, a photoresist (not shown) is formed on the main surface of the P-type silicon substrate 21, and then a first groove 22 having a depth of about three tones is formed by reactive ion etching using this as a mask. Next, after removing the photoresist, thermal oxidation is performed to form a film with a thickness of 1 on the surface of the substrate 21 including inside the first groove 22.
A thermal oxide film 23 of 0.000 mm is formed. Subsequently, after depositing a polycrystalline silicon film with a thickness of 40 μm over the entire surface along the first groove 22, for example, phosphorus is diffused and buttering is performed to form a low-resistance polycrystalline silicon layer 24. . A second groove 25 corresponding to the first groove 22 is formed inside this low resistance polycrystalline silicon layer 24 . Subsequently, molybdenum 26 having a thickness of 700 mm is deposited on the entire surface including the inside of the second groove 25, and a photoresist 27 is further formed on the entire surface using a spin code (as shown in FIG. 1(a)).

Next, the photoresist 27 is etched back in a plasma atmosphere using oxygen gas, so that the photoresist 27- partially remains only at the bottom of the second groove 25. Continuing,
Molybdenum-26 in a plasma atmosphere using Freon gas
to form molybdenum 26' masked with photoresist 27' only at the bottom of the second groove 25 (
Figure (b) shown). Subsequently, the remaining photoresist 27' is removed by etching in a plasma atmosphere using oxygen gas again (as shown in FIG. 2C).

Subsequently, thermal oxidation is performed at 900° C. for 30 minutes to form a thermal oxidation layer 1!28 with a thickness of about 800 nm on the surface of the low resistance polycrystalline silicon layer 24 doped with phosphorus. At this time, the oxide of molybdenum 26' sublimes, so the second groove 25
Molybdenum 26 with a film thickness of about 100 to 200 is on the bottom of the
” remains (as shown in Figure 2(d)).

Next, a high-resistance polycrystalline silicon layer 29 with a thickness of 4,000 wafers is deposited over the entire surface so as to be sufficiently buried in the second groove 25. Subsequently, in order to reduce the contact resistance, arsenic ions are implanted into the surface of the high-resistance polycrystalline silicon layer 29 at an acceleration energy of 40 keV and a dose of 3.times.101 s.alpha. As a result, although the surface region of the polycrystalline silicon layer 29 contains a large amount of arsenic, the arsenic does not reach the polycrystalline silicon layer 29 within the second trench 25 (as shown in FIG. 2(e)).

Subsequently, the polycrystalline silicon layer 29 is patterned and buried in the second groove 25 via the thermal oxide film 28, and the low resistance polycrystalline silicon layer 24 is formed via the molybdenum 26'' at the bottom of the second groove 25. A high-resistance element 30 connected to the high-resistance element 30 is formed.

Subsequently, heat treatment is performed at 800° C. to activate the arsenic introduced by ion implantation. Subsequently, after depositing an interlayer insulating film 31 on the entire surface, a contact hole 32 is opened, and an A2 film is further deposited on the entire surface, followed by buttering.
℃ electrode 33 is formed (as shown in FIG. 3(f)).

The semiconductor device shown in FIG. 1(f) has a P-type silicon substrate 2.
Thermal oxidation 112 is performed along the first groove 22 formed on the first main surface.
3, a low resistance polycrystalline silicon layer 24 buried through the
Molybdenum 26" formed at the bottom of the second groove 25 formed by the low resistance polycrystalline silicon layer 24, and a low resistance polycrystalline silicon layer 2 on the sidewall of the second groove 25 inside the second groove 25.
4 buried through a thermal oxide film 28 formed on the surface, and low resistance polycrystalline silicon through molybdenum 26''!!!2
4, and an AJ2 wiring 33 connected to the upper surface of the high resistance element 30.

According to such a semiconductor device, the high resistance element 30
is formed in the depth direction of the substrate 21 within the groove 25 of the electrode (
This area overlaps with the area required for the contact hole 32 with the Aj2 electrode 33) and its alignment margin, and the planar area has a value close to zero. Therefore, it is possible to significantly improve the miniaturization of elements and the reduction of cell size in future large-capacity static RAMs and the like. Further, the high resistance element 3o made of polycrystalline silicon is connected to the low resistance polycrystalline silicon layer 24 via molybdenum 26'', and is connected to the Aj2 wiring 33 through a surface region doped with a high concentration of arsenic. According to the method of the present invention, a semiconductor device having the above-mentioned effects can be manufactured by an extremely simple process.

Further, FIG. 2 shows the minimum structure including the other electrode of the high resistance element 30. That is, the semiconductor IAI in FIG. 2 is located at a position near one contact hole 32 of an interlayer insulating film 28 on a low-resistance polycrystalline silicon layer 24 extending over a main surface of a substrate 21 via a thermal oxide film 23. The structure is such that a contact hole 34 is opened in and an A2 electrode 35 connected to the low resistance polycrystalline silicon layer 24 via the contact hole 34 is formed. The semiconductor shown in Figure 2! 1iWl
It can be seen that the area near the high resistance element is mostly just the contact holes 32 and 34 and their alignment margins.

In the above embodiment, the low-resistance polycrystalline silicon layer 24 buried in the first groove 22 formed on the main surface of the substrate 21 was used as the low-resistance layer, but the present invention is not limited to this. For example, an N+ type expansion layer may be formed by forming and diffusing phosphorus, and this may be used as a low resistance layer.

Further, in the above embodiment, molybdenum was used as a metal layer for connecting the high resistance element 30 and the low resistance polycrystalline silicon layer 24, but this metal layer has a property that oxide sublimes during thermal oxidation. For example, chromium can be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly integrated semiconductor device in which the area of a high-resistance element is reduced, and a method for manufacturing such a semiconductor device through simple steps.

[Brief explanation of the drawing]

1(a) to (f) are cross-sectional views showing a manufacturing method for obtaining a semiconductor device having a high resistance element according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a high resistance element according to another embodiment of the present invention. FIGS. 3 and 4 are cross-sectional views of a semiconductor device having a conventional high-resistance element, respectively. 21...P-type silicon substrate, 22...first groove, 2
3.28... Thermal oxide film, 24... Low resistance polycrystalline silicon layer, 25... Second groove, 26.26', 26''.
...Molybdenum, 27,27-...Photoresist, 2
9... High resistance polycrystalline silicon layer, 30... High resistance element, 31... Interlayer insulating film, 32.34... Contact hole, 33.35... -AI2 electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4

Claims (7)

[Claims] (1) A low resistance layer formed on the main surface of the semiconductor substrate and having a groove on the inside, a metal layer formed on at least the low resistance layer at the bottom of the groove, and at least a surface of the low resistance layer on the side wall of the groove. The invention is characterized by comprising: a high resistance element embedded in a trench through an insulating film and connected to the low resistance layer through the metal layer; and a low resistance wiring connected to the upper surface of the high resistance element. semiconductor device. (2) The low resistance layer is a conductor layer that is embedded in a first groove formed on the main surface of the semiconductor substrate along the first groove with an insulating film interposed therebetween, and has a second groove inside. A semiconductor device according to claim 1, characterized in that: (3) The low resistance layer is a diffusion layer of a conductivity type opposite to that of the substrate, which is formed in the substrate along a groove formed on the main surface of the semiconductor substrate. Semiconductor equipment. (4) forming a low resistance layer having an inner groove on the main surface of the semiconductor substrate; forming a metal layer selectively on at least the low resistance layer at the bottom of the groove; and performing thermal oxidation. A step of forming an oxide film on the surface of the low resistance layer on the side wall of the trench, a step of burying a high resistance element in the trench, a step of introducing an impurity into the surface region of the high resistance element, and a step of forming an interlayer insulating film on the entire surface. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a contact hole and forming a low resistance wiring connected to an upper surface of the high resistance element. (5) After forming the first groove on the main surface of the semiconductor substrate, forming an oxide film on the substrate surface at least within the first groove, and further forming the first groove.
5. The method of manufacturing a semiconductor device according to claim 4, wherein a low resistance conductor layer having a second groove inside is formed by burying a conductor layer along the groove. (6) A patent claim characterized in that after a groove is formed in the main surface of a semiconductor substrate, an impurity of a conductivity type opposite to that of the substrate is introduced by thermal diffusion or ion implantation to form a low-resistance diffusion layer along the groove. A method for manufacturing a semiconductor device according to item 4. (7) The method for manufacturing a semiconductor device according to claim 4, wherein molybdenum or chromium is used as the metal layer.