JPH021922A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the making of a low resistant contact and the burying of a contact hole to be performed simultaneously even if the conductivities of semiconductor regions are different from each other by a method wherein a material to make contact and another material to be buried in the contact hole are respectively made of different materials such as tungsten silicide and polycrystalline silicon or BPSG film. CONSTITUTION:A photoresist 9 formed in the preceding process is released to deposit a silicon dioxide film using SiH4 by CVD process. First, BPSG films 12 are deposited using mixed gas of e.g., B2H6, PH3 and Si(OC2H5)4 by LPCVD process to be heat-treated in nitrogen. Secondly, the BPSG films 12 and the underneath silicon dioxide film are etched back by reactive ion etching process using mixed gas of CF4 and hydrogen to expose tungsten silicide 7 in the region excluding contact holes. Finally, aluminum 11 containing silicon is deposited by sputtering process to manufacture a semiconductor device by patterning the aluminum 11 and the tungsten silicide 7 in a specified shape using photoetching technology.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a buried hole on a semiconductor region.

[Conventional technology]

Conventionally, this type of buried contact is made by forming an element region and an n+ diffusion layer 5 in a predetermined region of a P-type silicon substrate 1, and then forming an insulating film 6 on the entire surface of the substrate, as shown in FIG. 3(a). , a contact hole is opened on the n+ diffusion layer 5. Next, by the LPCVD method, for example, PH1 and 3 i
Phosphorus-doped polycrystalline silicon 13 with a thickness of 1 μm was grown using a mixed gas of H4, and the phosphorous-doped polycrystalline silicon other than the contact hole portion was removed by using a mixed gas of OF and oxygen or by active ion etching. As shown in (b), the insulating film 7 is exposed. Finally, aluminum 11 containing, for example, 1% silicon is deposited to a thickness of 1 μm by sputtering and patterned into a predetermined shape by photolithography to obtain the semiconductor device shown in FIG. 3(c). Ta.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the phosphorus-doped polycrystalline silicon 13 is used as both the material for making contact with the n++ diffused layer 5 on the P-type silicon substrate 1 and the material for filling the contact hole, so the upper surface of the n+ layer is sufficiently low. Although contact resistance can be obtained, it becomes a rectifying contact on the P+ layer and cannot be used. Further, if poron-doped polycrystalline silicon is used instead of the above-mentioned phosphorus-doped polycrystalline silicon, a good contact can be obtained on the P+ layer, but on the contrary, a rectifying contact can be obtained on the n+ layer. In this way, if we try to realize a low-resistance contact using polycrystalline silicon doped with impurities of one conductivity type, and also to obtain a structure with a simple hole filling, it is said that it can only be applied to semiconductor devices of a single conductivity type. There were drawbacks.

If a buried contact is formed in a CMO8 type semiconductor device using conventional technology, the n-channel element region and the p-
It is necessary to form contact holes in the channel element region in completely independent steps from opening to filling them, which increases the number of steps and manufacturing costs. In this case, it is conceivable to fill the contact hole with non-doped polycrystalline silicon to obtain a resistive contact for both conductivity type semiconductor regions, but since non-doped polycrystalline silicon has a high resistivity, there is a large series connection with the contact hole. Resistance is formed, and the substantial contact resistance becomes large, making it unusable. As described above, the conventional technology has poor practicality for CMO8 type semiconductor devices.

〔the purpose〕

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and can simultaneously realize low-resistance contacts and burying of contact holes even in semiconductor regions of different conductivity types.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a high-melting point metal compound layer that makes electrical contact at the openings on regions of different conductivity types, and forming contact holes on each conductivity type region respectively with the same conductivity type. a step of adding impurity ions;
A step of forming an oxide layer in the contact hole and heat-treating it, a step of forming a contact hole burying layer on the substrate, a step of exposing a high melting point metal compound in an area other than the contact hole portion, and a step of forming wiring on the entire surface. After the metal film is formed, the metal film and the high melting point metal compound are patterned into a predetermined shape.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

As shown in FIG. 1(a), after forming a field oxide film 3 on a P-type silicon substrate 1 and separating the element regions,
An n well 2, an n++ diffused layer 5, and a p+ diffused layer 4 are formed at predetermined positions using an ion implantation method. After forming the insulating film 6 on the surface of the substrate 10, openings are formed in the insulating film 6 on the n++ diffused layer 5 and the P+ diffused layer 4 by photolithography. Next, the first
As shown in Figure (b), for example, a film with a thickness of 10
After depositing 0.00 tungsten silicide 7, a photoresist 8 with an opening on the P+ diffusion layer 4 is provided as shown in FIG.
, poron ions are implanted at a dose of I x 10"cm-2. After the photoresist 8 is peeled off, a photoresist 9 is again formed on the entire surface, and as shown in FIG. Only the resist is removed and the energy is 70 KeV, the dose is I
``Implant am-2 phosphorus ions.

After peeling off the photoresist 9, Si
A silicon dioxide film having a thickness of, for example, 1000 wafers is grown using H4 gas. Here, the silicon dioxide film is a cap to prevent impurities implanted from the tungsten silicide layer 7 from being extracted during heat treatment. 90
Heat treatment is performed for 5 minutes in nitrogen at 0° C. to activate and diffuse the implanted poron ions and phosphorus ions. After removing the silicon dioxide film with a buffered acid solution, a polycrystalline silicon film 10 is formed using SiH4 gas by the LPCVD method.
Deposit μm. At this time, it is desirable that the thickness of the polycrystalline silicon film is at least one-half or more of the length of the contact hole in the short side direction.

Further, the conductivity type impurity concentration of the polycrystalline silicon 10 may be arbitrary. The polycrystalline silicon film 10 is etched back using a mixed gas of CF 4 and oxygen or by active ion etching to expose the tungsten silicide 7 in areas other than the contact holes, as shown in FIG. 1(e). Thereafter, aluminum 11 containing 1% silicon was deposited to a thickness of 1 μm by sputtering, and photolithography was performed as shown in Figure 1(f).
As shown in FIG. 2, aluminum 11 and tungsten silicide 7 are patterned into a predetermined shape.

Next, a second embodiment of the present invention will be described using FIG. 2.

After obtaining the image shown in FIG. 1(d) in exactly the same manner as in the first embodiment, the photoresist 9 was peeled off and Si
A silicon dioxide film with a thickness of 1000 nm is grown using H4 gas. By the LPCVD method, for example, B 2 H
A total of 12 BPSG films 12 with a film thickness of 1 μm were formed using a mixed gas of S, P Hs and S i (OC2H5)4,
70 BPSG film 12 and the underlying silicon dioxide film are subjected to a heat treatment for reflowing the BPSG film 12 in nitrogen for 10 minutes at 900°C and activating the poron ions and phosphorus ions implanted into the contact hole.
The tungsten silicide is etched back using a mixed gas of 4 and hydrogen or by active ion etching to expose the tungsten silicide in areas other than the contact holes, as shown in FIG. 2(a). Aluminum 11 containing 1% silicon is deposited to a thickness of 1 μm by sputtering, and the aluminum 11 and tungsten silicide 7 are patterned into a predetermined shape by photolithography to obtain the semiconductor device shown in FIG. 2(b).

〔Effect of the invention〕

As explained above, the present invention uses tungsten silicide, polycrystalline silicon or BPSG as the contact material and the contact hole filling material.
By using separate materials such as membranes, CMO8
The present invention has the effect of providing a practical method for manufacturing buried contacts in type semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are longitudinal sectional views of a semiconductor device showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (b)
3 is a vertical sectional view of a semiconductor device showing the second embodiment in the order of steps, and FIGS. 3(a) to 3(c) are longitudinal sectional views of the semiconductor device showing the conventional technique in the order of steps. 1... P-type silicon substrate, 2... N-well layer, 3... Field oxide film, 4...
...P+ diffusion layer, 5...n+ diffusion layer, 6...
...Insulating film, 7...Tungsten silicide layer, 8, 9...Photoresist, 10...
... Polycrystalline silicon, 11 ... Aluminum wiring layer, 12 ... BPSG layer, 13 ...
Phosphorus-doped polycrystalline silicon. Agent Patent Attorney Susumu Uchihara (b)

Claims (1)

[Claims] a step of forming an opposite conductivity type region and a one conductivity type region on a one conductivity type semiconductor substrate; a step of forming an insulating film on the semiconductor substrate; and the insulating film on the opposite conductivity type region and the one conductivity type region. a step of forming an opening in the semiconductor substrate of one conductivity type, a step of forming a high melting point metal compound layer on the one conductivity type semiconductor substrate, a step of forming a buried layer to fill the opening, and a step of forming an opening in the area other than the opening. The method is characterized by comprising the steps of exposing a compound layer, forming a metal film for wiring on the semiconductor substrate, and patterning the metal film and the high melting point metal compound layer into a predetermined shape. A method for manufacturing a semiconductor device.