JPS61134793A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that displays images using a raster scan type image display device.

[Conventional technology]

Conventionally, the device shown in FIG. 5 has been known as this type of device. In the figure, 1 is the central processing unit (hereinafter referred to as CPU).
2 is an address latch circuit, 3 is a read/write control circuit, and 4 is a data switching circuit.
,3. ．． 4 is connected to the corresponding input/output port of CF'UI. 5 is an address switching circuit, 6 is an image display 'v
a frame memory in which display data is stored corresponding to the pixels at position t (not shown, but here on a CRT); 7 is a display data launch circuit that temporarily holds the display data sequentially outputted from the frame memory 6; Reference numeral 8 denotes a CRT controller which reads display data from the frame memory 6 at predetermined intervals and causes the display data to be displayed on the CRT via the display data launch circuit 7. On the other hand, 10 to 21 indicate the signal flow between the above parts, and 10.16 and 17.20 indicate the GPU
or the address from the CRT controller 8 to the frame memory 6, 12.19 is the display data read/written to the frame memory 6, 11 is the write signal 11a from the CPUI, the read signal 11b, and the resolution I for the CPUI.
(Ready) signals 11c and 13 are read control signals from the CRT controller 8, and 14 is a data switching control signal 14a output from the read/write control circuit 3 to the data switching circuit 4.

14b, 14c, and 15 are address launch signals for launching address 10 from the CPUI; 18 are write signals for writing data into the frame memory 6; and 21 are display data latch signals for launching display data from the frame memory 6.

Next, the operation of the conventional example configured as above will be explained. First, the case where CF) Ul writes data into the frame memory 6 will be described using the timing chart shown in FIG. At the rising edge t2 of the address launch signal 15 output from the read/write control circuit 3 based on the write signal 11a from the CPUI, the address 10 from the CPUI is latched in the address latch circuit 2. Similarly, at the rising edge t2 of the data switching control signal 14a output from the read/write control circuit 3,
Data 12 from CPU 1 is latched in data switch #I4. Then, the address 16 from the address latch circuit 2 is transmitted between 3'J1 (t z
~ts) is manually input to the frame memory 6. Further, the data 19 from the data switching circuit 4 also has the data switching control signal 14b outputted from the read/write control circuit 3 as "■",
" is output to the frame memory 6 during the period (ta to ta). Writing is then performed in the storage area of the frame memory 6 indicated by the above address by the write signal 18 output from the read/write control circuit 3.

Next, the case where the CPUI reads data from the frame memory 6 will be explained using the timing chart shown in FIG. Read signal from CPUI No. 1 1
At the rising edge tll of the address launch signal 15 output from the read/write control circuit 3 based on 1b, the address latch circuit 2 receives the address 10 from the CPU 1.
is latched. Note that the read/write control circuit 3 sets the ready signal lie for the CPUI to "L" at the falling edge tlo of the read signal 11b, thereby placing a wait on the CPUI. The address 16 from the address latch circuit 2 is input to the frame memory 6 during the period (1+□ to t1.) when the read control signal 13 output from the CRT controller 8 is "L", and the data is read out. The read data 19 is transmitted at the rising edge t13 of the data switching control signal 14C output from the read/write control circuit 3.
The data is latched in the data switching circuit 4. Lead
The write control circuit 3 changes the ready signal 11c to "H" at the rising edge tea of the data switching control signal 14c.
Notify the PU1 that it is ready and read the data 12.

On the other hand, when reading by the CRT controller 8, the read control signal 13 output from the CRT controller 8 is "H".
Address 2 from the CRT controller 8 during the period ``
0 is input to the frame memory 6 via the address switching circuit 5, and the data is read out. This read data 1
Reference numeral 9 indicates the CRT in the display data launch circuit 7.
Display data launch signal 2 output from controller 8
CR (not shown) is latched periodically at the rising edge of 1.
It is displayed on T.

[Problem that the invention seeks to solve]

In this way, in the conventional device, the CRT controller 8
By reading and writing data using the CPU during periodic reading of display data from the frame memory 6, periodic display of data on the image display device is made possible. However, when writing data from the CPU 1 to the frame memory 6, there is no problem because the address and data are latched by the address latch circuit 2 and the data switching circuit 4, but when the CPU 1 reads data from the frame memory 6, there is no problem. The CRT controller 8
cPUi is placed on wait until one cycle of reading data is completed and data is ready.
There was a problem in that the read speed of the UI was slow (=6-).

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that can perform high-speed reading by a CPU without impairing the functions of an image display apparatus controller for an image display apparatus.

[Means for solving problems]

The image processing device according to the present invention sets the display data read timing of the image display device controller that causes the image display device to display display data at a predetermined cycle within the above cycle based on the read/write access signal from the central processing unit. A readout control circuit is provided to delay the reading for a predetermined period.

[Effect]

In the present invention, when the display data readout timing of the image display device controller overlaps with the data read/write timing by the central processing unit, the readout control circuit performs readout data within the same period based on the access signal from the central processing unit. It is read out with a delay of a period.

〔Example〕

The present invention will be explained below based on the embodiments shown in FIGS. 1 to 4. Note that the same reference numerals are used for the same or equivalent parts as in the conventional example, and the explanation thereof will be omitted.

FIG. 1 is a block diagram showing the overall configuration of this embodiment,
As shown in the figure, in this embodiment, the address launch circuit 2 and read/write control circuit 3 of the conventional device are not provided, and a read control circuit 9 is newly provided. Address 10 from the CPUI is directly input to the address switching circuit 5, and the address switching circuit 5
．． Data switching circuit 4. The frame memory 6 and the newly provided readout control circuit 9 receive the write signal 1 from the CPUI.
1a or the read signal 11b. On the other hand, 22 is a latch enable signal outputted from the readout control circuit 9 to the display data launch circuit 1iR7 indicating the launch availability state, and 23 is a latch enable signal outputted from the ICRT controller 8 to the readout control circuit 9 with a different phase and pulse width. Type successive control n signals 23a, 23
b, 24 is a ready signal output from the read controller=8-path 9 to the CPUI.

Note that the readout control circuit 9 in this embodiment has a second
As shown in the figure, NAND gate 100°104.10
5 and D type flip-flop 101゜102.103 and A
It is composed of an ND gate 106. Note that Ild is the output of the NAND gate 100, that is, a CPU access signal indicating the presence or absence of either the write signal 11a or the read signal 11b, and 25 is the NAND gate 104.
shows the output signal of

Next, the operation of this embodiment configured as above will be explained. First, reading and writing data to and from the frame memory 6 using the CPUI will be explained using FIG. When writing data, a write signal 11a is sent from the CPU to the address switching circuit 5. It is output to the data switching circuit 4 and the frame memory 6, and when this signal 11a is L'', the CPU
The blank address 10 is input to the frame memory 6 via the address switching circuit 5, and the data 12 from the CPU is input to the frame memory 6 via the data switching circuit 4, and data writing is performed. On the other hand, when data is not read, the address 10 from the CPU 1 is similarly read during the period when the read signal 11b is "■,".
is input to the frame memory 6 via the address switching circuit 5, and the data is read out. The read data is read into the CPUI via the data switching circuit 4.

Next, data reading by the CRT controller 8 will be explained in detail using the circuit diagram shown in FIG. 2 and the timing charts shown in FIGS. 3 and 4. First, when the CPUI accesses the frame memory 6 for reading or writing as shown in the timing chart of FIG. A case where reading is to be performed now will be explained. Rise tl of access signal lid. . Then, the control signal 23 is output one after another in the D-type flip-flop 101.
have lunch a. Since this latch data is "L", it is stored that the access signal lid has come from the CPUI. The Q output of this D-type flip-flop 101 is latched at the rising edge t 101 of the read-only J'In signal 23a in the next-stage D-type flip-flop 102, and furthermore, the Q output of this D-type flip-flop 102 is It is latched in the D-type flip-flop 103 at the next stage at the next rising edge t104 of the read control signal 23a. The signal 25 can be obtained by NANDing the Q output of the D-type flip-flop 102 and the Q output of the D-type flip-flop 103. In addition, the Q output of the flip-flop 103 of the above type “
D type flip-flops 101 and 102 by I7''
is set. Then, the launch enable signal 22 is obtained by ANDing the signal 25 and the read control signal 23b. In the display data latch circuit 7, the display data read from the frame memory 6 is latched by the display data latch signal 21 only when the latch enable signal 22 is "I7". In this case, the incorrect display data (C'PUD) is latched at the usual timing t1゜1, but normally "I]"
By setting the latch enable signal 22 to "L", the timing tea is delayed by a predetermined period within the same cycle.
3, the correct display data (CRTI) 1) can be latched.

Note that at this read timing t103, the CPU
Since it would be a problem if access was required from the CPU, the ready signal 24 is used to put a wait on the CPU only in this case. The next display data (CRTr) 2) is tl as usual. It is latched at 4. The display data launched in this way is displayed at t10 immediately before the CRT address is switched.
The value of 3 is considered valid and sent to the next stage, that is, the CRT side.

Next, as shown in the timing chart of FIG.
When J1 accesses the frame memory 6, the read control signal 23a is activated at the rising edge of the access signal 11d.
is “H”, that is, already. RT:I/)t:1
-78. :Yo, engineering, ka, 1. Wow 1.1 Go will be explained. At the rising edge tllo of the access signal lid, the read control signal 23a is activated in the D-type flip-flop 101.
have lunch. Since this latch data is "■1", the Q output of the D-type flip-flop 101 does not change.

Therefore, the output signal 25 of the NAND circuit 104 remains "H", and the latch enable signal 22 becomes the read control signal 2.
3b remains as is. In this case, unlike the case of FIG. 3, correct display data (CRTDI) can be launched at the usual read timing tIIZ. The latched display data is sent to the CRT side with the value tIll immediately before the CRT address switched as valid.

〔Effect of the invention〕

As explained above, according to the present invention, the display data readout timing of the image display device controller that causes the image display device to display display data at a predetermined period is determined based on the read/write access signal from the central processing unit. By providing a readout control circuit that delays the readout for a predetermined period within the image display device, an image processing device that can perform readout by the CPU at high speed can be obtained without impairing the function of the image display device controller for the image display device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention, and FIG. 2 is a circuit diagram of a readout control circuit in the above embodiment. 3 and 4 are timing charts showing the operation of the above embodiment, respectively, FIG. 5 is a block diagram showing an example of the conventional device, and FIGS. 6 and 7 are timing charts showing the operation of the above conventional example, respectively. It is. DESCRIPTION OF SYMBOLS 1... Central processing unit (CPU), 6... Memory, 7... Display data latch circuit, 8... Image display device controller, 9... Readout control circuit. In addition, in the figures, the same reference numerals are used for the same or corresponding parts. Agent: Masu Oiwa 111 (and 2 others) volunteered to write the procedural amendment) 20 Name of the invention Image processing device 3, person making the amendment Relationship to the case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 5, Drawing subject to amendment. 6. Contents of amendment (11 drawings and Figure 2 will be amended as shown in the attached sheet.)

Claims (1)

[Claims] a memory that stores display data to be displayed on the image display device; a central processing unit that outputs read/write access signals to read and write display data to the memory; and a central processing unit that reads display data from the memory and processes the display data. In an image processing device equipped with an image display device controller that causes the image display device to display the display data at a predetermined period via a latch circuit, the display data read timing of the image display device controller is determined by an access signal from the central processing unit. An image processing device characterized in that it is provided with a readout control circuit that delays by a predetermined period within the above cycle.