JPS61139990A - Serial access memory - Google Patents

Abstract

PURPOSE:To eliminate the effective access time of a readout cycle by providing a logical circuit which activates an internal control signal in readout operation before an external control signal is activated and outputs starting address data. CONSTITUTION:The logical circuit consists of an AND gate 11 which ANDs a readout setup completion signal phiE and the external control signal phiW, an inverter 12 which inverts the external control signal phiC, an OR gate 10 which ORs outputs of the gate 11 and inverter 12 and outputs the internal control signal phiC. The external control signal phiI is activated, the signal phiE is activated and the signal phiC is activated before the signal phiR is activated for the 1st time, and information on the starting address of a data register is read out and outputted to an output terminal OUT before the signal phiR is activated for the 1st time. Therefore, when the signal phiR is activated for the 1st time, the information on the starting address of the register 2 shifts and is outputted to the terminal OUT, so that the substantial access time is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a serial access memory in which data is serially read and written by an internal signal generated in synchronization with an external control signal.

[Conventional technology]

2. Description of the Related Art Recently, semiconductor memory circuits (hereinafter referred to as serial access memories), which are characterized by serial reading and writing, have been used as storage elements for audio signals, image signals, and the like.

FIG. 4 is a schematic diagram of a conventional example of this type of serial access memory having a memory cell matrix l of m×n bits. The n-bit data register 2 is connected to the memory cell 1 matrix 1 at a ratio of 1 bit per pair of digit lines, and receives an external control signal φ via an inputter 4.
Memory cell matrix 1 and data register 2 from iK
Data is not transferred between the two.

At the time of reading, the contents of the n-bit data register 2 are sequentially selected by the n-bit shift register 8 driven by the external control signal φRIIC via the inverter 1, and serially outputted to the output terminal OUT KV through the output circuit 7. On the other hand, when writing, the contents of external data ]) iM are
Inverters 5 and 5 are controlled by external control signals φR1 and φW respectively.
The data are sequentially selected by the n-bit shift register 8 via the Nant gate 6 and serially written into the n-bit data register 2. .

FIGS. 5 and 6 are time charts showing the above read and write cycles, respectively. −Read cycle (
When external control signal φI is activated (transitions from logic IH level to lL'' level) at time t in FIG. 6), IH signals are applied to data 9 register 2 by inverter 4, and row selector line ( (not shown) goes to the IHl level and data is transferred from the memory cell matrix 1 to the data register 2. At this time, the shift register 8 is simultaneously initialized via its reset line (not shown). After that, at time t, K, external control signal φ
R is activated (transition from logic IH level to @L″ level)
Then, internal control signal ψ0 is activated (transitions from GND level to power supply level) via inverter 5. When the internal control signal ψ0 is activated, the information D1 from the data register 2 selected by the lift register 8 is outputted from the output circuit 7 to the output terminal OUT via the Hori bus 9 after a certain period of time TAO has elapsed. At this time, the write-related external control signal φi must be inactive (logic 1H'' level).The above cycle is then repeated to obtain information.

... is output to the output terminal OUT.

On the other hand, in the write cycle (FIG. 6), external control signal φ1. φR and internal control signal ψ. Activation is performed at 5 as shown in the figure, and external input data D! xl *
D! It... is sequentially written into the n-bit data register 2 via the input circuit 8. Thereafter, one data transmission is performed from data register 2 to memory cell matrix b.

[Problem that the invention seeks to solve]

By the way, access time T person 0 in i output cycle
Ideally, it is desirable that it be zero, but in reality it is not zero because it is easily influenced by process conditions, power supply voltage, ambient temperature, etc.

An object of the present invention is to provide a serial access memory that reduces the effective access time to zero in a read cycle.

Means for Solving Problem c] The present invention focuses on the fact that in a serial access memory, the next address to be selected is already known (the address is updated sequentially), and the present invention provides the following advantages during a read operation.

a logic circuit that activates the internal control signal before the external control signal is activated, and outputs the data at the first address before the external control signal is activated for the first time; The data at the address is output by the internal control signal before being activated in response to the read cycle. The effective access time for access is set to zero.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a serial access memory of the present invention. In this embodiment, in the conventional example shown in FIG. 4, a read ready signal ψ is added, and the read ready signal ψ is ANDed with an external control signal φ□ instead of the inverter 5 of FIG. An inverter 12 inverts an external control signal φ, and an OR gate 10 that takes the logical sum of the AND gate 11 and the inverter 1z and outputs an internal control signal φb. AND gate 11 mentioned above. An internal control signal ψ is the output of a logic circuit consisting of a NAND game) 11 and an OR gate 10. is when the external control signal φ is activated,
Or external control, signal φ1 is inactive (logic 1H)
” level) and the read ready signal ψ is active <U
Activates when the source bell).

FIG. 2 is a time chart of a read cycle of the serial access memory shown in FIG. External control signal φI is activated at time t1, and external control signal φR is first activated at time t, at time t! The read ready signal ψI is activated (of course, the external control signal φ7 is inactive).
, internal control signal ψ.

Before the time t when the external control signal φR is activated and the external control signal φR is activated for the first time, the information D1 at address 0 of the data register 2 is read out and outputted to the output terminal OUTK. Therefore, when the external control signal φ8 is activated for the first time at time t, the information D1 at address θ of the data register 2 is shifted and outputted to the output terminal OUTK, and the actual access time becomes zero. Activation of external control signal φR at time t activates internal control signal φb, and the information at the next address, ie, address 1, is read out. Similarly, information D3 at address 2 is read out by activation of external control signal φR at time t4...K.

FIG. 8 is a time chart of write times in the serial access memory of FIG. 1. Read ready signal ψB
Even if the internal control signal ψυ is activated at time t, the internal control signal ψυ is not activated, so the read ready signal ψ3. It is possible to perform exactly the same write operation as in the conventional example shown in FIG. 4 without being affected by this.

FIG. 7 shows a conventional example of a serial access memory constructed with a column decoder 18 and a column counter 14 instead of the n-bit left register 8 of FIG. However, the present invention can also be applied to this serial access memory.

〔Effect of the invention〕

As explained above, in the present invention, K during the read operation.

By providing a logic circuit that activates the internal control signal before the external control signal is activated and outputs the data at the first address before the external control signal is activated for the first time, the effective access time of the read cycle is reduced to zero. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the serial access memory according to the present invention, FIGS. 2 and 8 are time charts during read and write operations of the embodiment of FIG. 1, and FIG. 5 and 6 are time charts of read and write operations, respectively, in the conventional example of serial access memory in FIG. 4, and FIG. 7 is a block diagram of another conventional example of serial access memory. In block diagram. be. ψ0・・・・・・・・・・・・Internal control signal. φ1. φW, φR...External control signal. 10...scream old...or game)t
711・・・・・・・・・・・・And gate. 1z・・・・・・・・・・・・Inverter. Figure 4

Claims (1)

[Claims] In a serial access memory in which data is serially read and written by an internal control signal generated in synchronization with an external control signal, the internal control signal is activated before the external control signal is activated during a read operation. . A serial access memory comprising a logic circuit that outputs data at a leading address before the external control signal is activated for the first time.