JPS61150060A - デ−タ処理装置 - Google Patents
デ−タ処理装置Info
- Publication number
- JPS61150060A JPS61150060A JP28081884A JP28081884A JPS61150060A JP S61150060 A JPS61150060 A JP S61150060A JP 28081884 A JP28081884 A JP 28081884A JP 28081884 A JP28081884 A JP 28081884A JP S61150060 A JPS61150060 A JP S61150060A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- processor
- system bus
- memory bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
- Processing Or Creating Images (AREA)
- Image Processing (AREA)
- Advance Control (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28081884A JPS61150060A (ja) | 1984-12-24 | 1984-12-24 | デ−タ処理装置 |
| CA000497467A CA1254662A (en) | 1984-12-24 | 1985-12-12 | Image data processor system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28081884A JPS61150060A (ja) | 1984-12-24 | 1984-12-24 | デ−タ処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61150060A true JPS61150060A (ja) | 1986-07-08 |
| JPH0542703B2 JPH0542703B2 (2) | 1993-06-29 |
Family
ID=17630403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28081884A Granted JPS61150060A (ja) | 1984-12-24 | 1984-12-24 | デ−タ処理装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150060A (2) |
-
1984
- 1984-12-24 JP JP28081884A patent/JPS61150060A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542703B2 (2) | 1993-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61150059A (ja) | デ−タ処理装置 | |
| WO1987002488A1 (fr) | Systeme de memoire multiport | |
| EP0409285B1 (en) | Method and apparatus for data transfer between processor elements | |
| JPS618785A (ja) | 記憶装置アクセス制御方式 | |
| JPS61182157A (ja) | 画像処理装置及び相互通信バス装置 | |
| WO1988003292A1 (en) | Data alignment system | |
| US3703707A (en) | Dual clock memory access control | |
| JPS61150058A (ja) | デ−タ処理装置 | |
| TW487925B (en) | Multi-ported memory with asynchronous and synchronous protocol | |
| JPS61151775A (ja) | デ−タ処理装置 | |
| JPS61150060A (ja) | デ−タ処理装置 | |
| US6483753B1 (en) | Endianess independent memory interface | |
| JP2781550B2 (ja) | 並列処理計算機 | |
| CA1254662A (en) | Image data processor system and method | |
| TW526427B (en) | Access to a collective resource | |
| JPS6367702B2 (2) | ||
| SU1133622A1 (ru) | Буферное запоминающее устройство | |
| JPS6019258A (ja) | 記憶装置 | |
| KR930003993B1 (ko) | 다중처리기 시스템에서의 데이타 전송방법 | |
| JPS5953939A (ja) | リアルタイム用メモリ装置 | |
| JPS5831437A (ja) | デ−タ受信装置 | |
| JPH0370052A (ja) | アドレス変換回路、メモリコントロール装置、情報処理装置、および、記録装置 | |
| JPS582963A (ja) | メモリ方式 | |
| JPH03232044A (ja) | 主記憶バス | |
| JPS63298434A (ja) | シ−ケンシャルメモリ回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |