JPS61155865A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To reduce a voltage error and to limit a current by providing a differential amplifier, a capacitor, a switch, etc. CONSTITUTION:The differential amplifier 4, the capacitor 5, the switch 1, etc., are provided. Then, an input terminal 3 is connected to the uninverted input terminal of the amplifier 4. Then, a capacitor 5 is interposed between the inverted input terminal of the amplifier 4 and a reference potential and an output terminal 6 is led out from the inverted input terminal. Further, a current source 7 and the switch 1 for charging the capacitor 5 are interposed in series between a power source VCC and the amplifier 4. The switch 1 is controlled with the output of the amplifier 4. Namely, the switch is off when Vin<=Vp and on when Vp<Vin. In this case, Vin is an input signal and Vp is the charging voltage of the capacitor 5. Consequently, when Vin>Vp, the switch 1 is turned on to charge the capacitor 5 with a current value I0. When Vin<=Vp, on the other hand, the current value is zero and the capacitor 5 is held at the voltage Vp. Therefore, the maximum peak voltage of the input signal is held at the terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a peak hold circuit for holding a value of a signal signal #'i.

[Technical background of the invention]

In general piezoelectric circuits, the AGC (automatic gain control) circuit, which functions to keep the signal amplitude constant, detects and holds the maximum amplitude of the signal after gain control, or inserts a reference into the signal φ after gain control. The signal, that is, the Panut signal, is extracted, its swing II/Avi-detected, and held. Then, a feedback tube is connected to the AGC amplifier to control the gain of the system according to this held coefficient level. A peak hold circuit (peak value holding circuit) is used to hold the detected signal amplitude.

The simplest such peak hold circuit has a configuration as shown in FIG. 2, for example. That is, the input signal V in is passed through the terminal IN to the NPN transistor Q,
give to the base of The collector of transistor Q1 is connected to the power supply Vcc, and the emitter is connected to ground potential via terminal OUT and capacitor c1. In this way, the peak value vp of the input signal Vin can be output from the terminal IN. Here is the transistor Q.

For simplicity, when vix>Vmgo, transistor Q1 is on, and VBIC<VBI. It is idealized and considered that the transistor QtFi is off when . Therefore, Vin>VP”V
When the voltage is 0, the transistor Q1 turns on and current flows into the capacitor C1, increasing the voltage Vp at the terminal OUT to Vin.
- Increase with Vmgo4. Vin=vp+
The moment the voltage reaches VBIO, transistor Q is turned off and the voltage at terminal 2 stops rising. When Vin<Vp+Vilo, the transistor Qs Fi turns off and the capacitor Cti
;tThe peak voltage Vpt is maintained. In this way, the voltage - which depends on the peak value of the terminal 2KF1 input signal
Vp = max V in -VBKO is maintained.

[Problems with background technology]

However, the peak hold circuit shown in FIG. 2 has a voltage error in the on-voltage VBIO of the transistor.
Also, the V of the actual transistor! II! The j-I C characteristics are diode characteristics, and the input voltage Vin is O<V.
Since the region where in -vp < Vivo is a microcurrent region, the peak voltage Vp may vary depending on the frequency of the input signal, etc.
is likely to become unstable or inaccurate. Furthermore, since there is no current limit in the transistor, it is easy to hold the peak of noise, and when the amplitude of the input signal changes suddenly, a large current flows instantaneously, which can cause problems such as spike-like noise on the power line. Ta.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a peak hold circuit that has few voltage errors and is capable of current limitation.

[Summary of the invention]

The present invention provides an input signal to one input of a differential amplifier,
A capacitor tube is inserted between the other input and the reference potential, an output terminal is derived from this other input, a current source and a switch are connected in series, and this switch is connected to the output terminal of the differential amplifier. This is characterized in that the peak value of the input signal is held in the capacitor by controlling the input signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below in detail with reference to the block diagram shown in FIG. 1. An input terminal 3 is connected to a non-inverting input of a differential amplifier 4. A capacitor 5 is inserted between the inverting input of the differential amplifier 40 and the reference potential, and an output terminal 6 is derived from the inverting input. Furthermore, a current source 7 for charging the capacitor 5 and a switch 1 are inserted in series between the % source vCC and the inverting input of the differential amplifier 40.

Note that the output of the switch IFi differential amplifier 4 is controlled as follows.

That is, when Vin≦Vp, Vp is off (when Vin is on, however, Vpti is on, but the charging voltage of capacitor 5 is Voltage Vpf: Vin
Raise at t. Also, when Vin≦Vp, the current value is 0.
The capacitor 5 maintains the peak voltage Vp as it is.

Therefore, the maximum peak voltage m of the input signal is applied to the output terminal 6.
az V i n is retained.

FIG. 3 shows a zero path that maintains the minimum peak value min Min of the input signal based on the same principle as FIG. 1. In this case, if the input terminal 3'Ik is connected to the inverting input of the differential amplifier 4, and the output terminal 6 is connected to the non-inverting input, a capacitor 5 is connected between this non-inverting input and the power supply Vcc. A current source 7 and a switch 1 are connected in series between the current source 7 and the reference potential.

Furthermore, the output of the differential amplifier is controlled so that when Vin≦Vp, the switch 1't is turned on, and when Vp<Vin, the switch 1 is turned off.

FIG. 4 is a circuit diagram showing a specific example of the present invention corresponding to FIG. 1. That is, the emitters of transistors 8.9 are connected in common and connected to a reference potential via a current source 1ot-. The pace of the transistor 8 is connected after the input terminal sK, and the collector is connected to the power supply Vcc via the resistor 11.

Further, the base of the transistor 90 is connected to the output terminal 6, a capacitor 5 is inserted between this pace and a reference potential, and this pace is further connected to the collector of the transistor 12. The pace of this transistor 12 is connected to the collector of the transistor 8, and the emitter is connected to the power supply VccK via a resistor 13.

Here, the pace current of the transistor is ignored as it is sufficiently small compared to the collector current. Therefore, the transistor 8.9d constitutes a differential amplifier, and the voltage generated across the resistor 11 is converted into a current value by the resistor 13 and the transistor 12, and the capacitor 5 connected to the pace VC of the transistor 9 is charged. This circuit obtains the peak value of the signal Vin inputted to the input terminal 3 from the terminal 6.

In this circuit, the potential difference between terminal 3 and terminal 6 is Δ
When the charging current of the capacitor 5, that is, the collector current of the transistor 12 is Ic, the voltage across the resistor 11 is equal to the sum of the collector voltage of the transistor 120 and the voltage across the resistor 130, so the following equation (1) holds true. do.

K: Boltzmann constant, q: electron charge.

T: Absolute temperature Is: Reverse saturation current of transistor, ■3. ．． : Current of constant current source 10, R11e R1
11: In the six values of the resistor 11 and 13 and in the operating current range, the pace and collector voltage of the transistor 12 are set to a substantially constant value VBIO, Ic, and vTlnTi-=v■o, then the following equation (2) is given.

Here, the relationship between Win-VP and Windows is as shown in FIG. 5, for example. Here, the region where Vin-vp is O to vN is a region where the transistor 12 is not completely turned off or turned on. Furthermore, with this characteristic, when Δv=00, Ic=
The current idea is that O. If this condition is found from the equation (2), the following equation (3) is given.

Also, from equation (2), the transconductance at the current limit value 0 and Δ■;o < 9 I e ) Δy ==
When geΔV is determined, the following equations (41, (51) are given.

Figure 6 is an improved version of the circuit shown in Figure 4, in which the output of the differential amplifier is not a single-ended type as shown in Figure 4, but is applied as a differential type between the Beine emitters of the transistor 12. 0 that increases transconductance
Collector current Ic of transistor 12 in this circuit
is given by the following equation (6).

-Vi+go) ・・・・・・・・・・・・(6)
However, Ro is the value of the resistor 14, and is the value of the current source 10. When Δv=0, the condition for Ic=O is given by the following (7).

Therefore, from equation (6), the current limit value and ΔV ==
Transconductance (e I C) Δ at 0
When y=6eΔV is determined, K is obtained as shown in the following equations (8) and (9).

Here, by comparing the above-mentioned equations (5) and (9), it is clear that the transconductance of the circuit has increased.

Figure 7 corresponds to Figure 1 and is a peak hold circuit using NMO8) range meta.O that is, N11MO8)
Rangemetal z5.16 constitutes a differential amplifier, PIIM
O8) The gain is increased using a range meter 17°18 active load.

input layer 19
The gate of the MO8II inducer 16 is connected to the output terminal 20, and a capacitor zlt is inserted between this gate and the reference potential. Then, the sources of the MOS transistors 15°16 are connected in common, and the current source 22t-
Connect to the reference potential via. Further, the gate of the P-type MO 8) range metal 23 is connected to the drain of the MOS) range metal 15, and the drain is connected to the output terminal 20. Furthermore, the source of this MOS) Range Meta 23 is connected to each gate of MOS) Range Meta 17 and 18 and MOS) Range Meta J
Connect to the drain of 8.

Then, the input signal V in given to the holder 19 is input to the terminal 2.
When the peak pressure Vp, which is held at 0, becomes higher, the gate voltage of the transistor 23 becomes 17. N-7 to 2
The voltage increases and supplies charging current to capacitor 2. In this way, the peak value of the signal input to the terminal 19 can be taken out from the terminal 2σ). The drain current of the transistor 23 is supplied from the power supply Vcc through the transistor 18, but as this current increases, the y, - potential of the transistor 23 also decreases, and is fed back to the voltage between the gate and Saone, limiting the current. It has a function.

That is, in the configuration shown in FIG.
8 is applied between the gate and source of the transistor 23, a charging current is applied from the drain of the transistor 23 to the capacitor 21, and this voltage is fed back to the gate of the transistor 16. Furthermore, if it is constructed with a MOS (MOS) range metal, it is particularly suitable for integrated circuits, and it is easy to incorporate the hold capacitor into an integrated circuit element by taking advantage of its good hold characteristics, making it extremely useful. .

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a circuit with a relatively simple configuration that has no voltage error due to the configuration of the voltage return 11M and can easily perform current limitation. Furthermore, it is suitable for the present invention's semiconductor integrated circuit, and can be configured with either bipolar transistors or MOS transistors, and has special features.
When a MOS transistor is used, since the IC can obtain good hold characteristics, it is possible to provide a peak hold circuit in which a hold capacitor can be easily incorporated into an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a circuit diagram showing an example of a conventional peak hold circuit, FIG. 3 is another six block diagram explaining the present invention in detail, and FIG. 4 is a block diagram explaining the present invention in detail. 1 is a circuit diagram showing a specific example corresponding to FIG. 1, FIG. 5 is a diagram explaining the characteristics of the configuration shown in FIG. 4, and FIGS. 6 and 7 are diagrams showing other embodiments of the present invention. FIG. 1...Nutsch, 4...Differential width amplifier, 5...Capacitor, 1...Current source. Applicant's attorney Suzue Takehiko No. 5 [4th v! JwI7 figure

Claims (5)

[Claims] (1) A differential amplifier to which an input signal is applied to one input, a capacitor that outputs the charging voltage as a peak hold value and is applied to the other input of the differential amplifier, and a current source that charges this capacitor in series. and a switch connected and controlled by the output of the differential amplifier. (2) The peak hold circuit according to claim 1, which holds the maximum peak value of the input signal. (3) A peak hold circuit that holds the minimum peak value of an input signal in the device described in claim 1. (4) In the item described in claim 1, MOS
A peak hold circuit composed of transistors. (5) A peak hold circuit according to claim 4, which is an integrated circuit and has a capacitor built into the integrated circuit element.