JPS61166671A - 複合プロセツサ制御方式 - Google Patents

複合プロセツサ制御方式

Info

Publication number: JPS61166671A
Authority: JP; Japan
Prior art keywords: processor; bus; state; arbitration; memory device
Prior art date: 1985-01-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

JP799385A

Other languages

English (en)

Japanese (ja)

Other versions

JPH0156420B2 (2

Inventor

Naoki Koizumi

直樹小泉

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Panafacom Ltd

Original Assignee

Panafacom Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-01-19

Filing date

1985-01-19

Publication date

1986-07-28

1985-01-19 Application filed by Panafacom Ltd filed Critical Panafacom Ltd

1985-01-19 Priority to JP799385A priority Critical patent/JPS61166671A/ja

1986-07-28 Publication of JPS61166671A publication Critical patent/JPS61166671A/ja

1989-11-30 Publication of JPH0156420B2 publication Critical patent/JPH0156420B2/ja

Status Granted legal-status Critical Current

Links

239000002131 composite material Substances 0.000 title 1
230000010365 information processing Effects 0.000 claims description 2
238000010586 diagram Methods 0.000 description 10
238000000034 method Methods 0.000 description 5
240000002853 Nelumbo nucifera Species 0.000 description 3
235000006508 Nelumbo nucifera Nutrition 0.000 description 3
235000006510 Nelumbo pentapetala Nutrition 0.000 description 3
238000007796 conventional method Methods 0.000 description 2
244000269722 Thea sinensis Species 0.000 description 1

Landscapes

Multi Processors (AREA)
Bus Control (AREA)

JP799385A 1985-01-19 1985-01-19 複合プロセツサ制御方式 Granted JPS61166671A (ja)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
JP799385A JPS61166671A (ja)	1985-01-19	1985-01-19	複合プロセツサ制御方式

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP799385A JPS61166671A (ja)	1985-01-19	1985-01-19	複合プロセツサ制御方式

Publications (2)

Publication Number	Publication Date
JPS61166671A true JPS61166671A (ja)	1986-07-28
JPH0156420B2 JPH0156420B2 (2)	1989-11-30

Family

ID=11680925

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP799385A Granted JPS61166671A (ja)	1985-01-19	1985-01-19	複合プロセツサ制御方式

Country Status (1)

Country	Link
JP (1)	JPS61166671A (2)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS63257051A (ja) *	1987-04-15	1988-10-24	Hitachi Ltd	マルチコンピユ−タシステム
US6143404A (en) *	1996-12-20	2000-11-07	Technic Gum	Lining for a driving or return drum of a conveyor belt

1985
- 1985-01-19 JP JP799385A patent/JPS61166671A/ja active Granted

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS63257051A (ja) *	1987-04-15	1988-10-24	Hitachi Ltd	マルチコンピユ−タシステム
US6143404A (en) *	1996-12-20	2000-11-07	Technic Gum	Lining for a driving or return drum of a conveyor belt

Also Published As

Publication number	Publication date
JPH0156420B2 (2)	1989-11-30

Similar Documents

Publication	Publication Date	Title
EP0165600B1 (en)	1991-11-21	Input/output bus for computer
JPH061458B2 (ja)	1994-01-05	共有母線のための分配仲裁装置および方法
US5239631A (en)	1993-08-24	Cpu bus allocation control
EP0132157A2 (en)	1985-01-23	Data processing system having dual processors
US5901295A (en)	1999-05-04	Address and data bus arbiter for pipelined transactions on a split bus
US5301282A (en)	1994-04-05	Controlling bus allocation using arbitration hold
NZ228785A (en)	1991-04-26	Microcomputer with cache subsystem: preempt signal limits access time of peripheral unit
JPH05197671A (ja)	1993-08-06	マスター・スレーブ通信方法
JP3583183B2 (ja)	2004-10-27	データ処理装置
JPS61166671A (ja)	1986-07-28	複合プロセツサ制御方式
US5931931A (en)	1999-08-03	Method for bus arbitration in a multiprocessor system
JPH09501249A (ja)	1997-02-04	高速／低オーバーヘッド・バス調停機構およびシステム・バスの調停方法
JPH0581178A (ja)	1993-04-02	パイプラインバス
JPH1125036A5 (2)	2005-08-18
JPH06266657A (ja)	1994-09-22	情報処理装置
JP2556290B2 (ja)	1996-11-20	バス調停装置
JPH0525135B2 (2)	1993-04-12
JPH04128957A (ja)	1992-04-30	マルチプロセッサシステムにおける共有資源の排他制御方法
JPS63236153A (ja)	1988-10-03	記憶装置
JPH0666060B2 (ja)	1994-08-24	バス優先権制御方式
JP2976358B2 (ja)	1999-11-10	バス獲得制御方式
JPH05151145A (ja)	1993-06-18	システムバス制御装置
JPH01159754A (ja)	1989-06-22	データ処理方式
JPH06161951A (ja)	1994-06-10	バス制御方式
JPH03240151A (ja)	1991-10-25	データ転送制御方式