JPS6117399B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image receiving apparatus that can be used in a system that multiplexes and transmits still image signals during the vertical retrace period of a television signal.

Recently, systems for multiplexing and transmitting still image information such as character information or simple pattern information onto television signals have been developed by dividing the still image to be transmitted into many picture elements vertically and horizontally and scanning them sequentially. It has been proposed to extract horizontal lines or vertical columns of image signals, superimpose them during the vertical retrace period of a television signal, and transmit them. To receive such a still image signal, first extract the image signal multiplexed with the television signal, store it in a predetermined order in a memory with a capacity of one to several lines, and then scan the cathode ray tube. The image is read out from this memory in synchronization with the image data and displayed as a still image on the cathode ray tube.

As a transmission method for such still image signals,
Conventionally, two methods have been proposed: a horizontal feed method and a vertical feed method, and a mixed method in which signals from both types are mixed and transmitted is also being considered. Here, the horizontal feed method is to scan a still image in the horizontal direction and transmit the image signal for one line, or an integral multiple or fraction thereof.
The vertical feed method is a method in which a still image is scanned in the vertical direction, image signals are extracted, and only such image signals are transmitted. Further, the mixed method is a method in which a horizontally-feeding image signal and a vertically-feeding image signal are alternately switched for each fixed field, mixed, and transmitted on the same channel of television signals. However, in this mixed method, the image signal of the horizontal feed method is the same as the case of single transmission of the horizontal feed method, so it can be treated the same as the case of single transmission, but the image signal of the vertical feed method is 1 compared to the case of independent transmission using the vertical feed method.
Since it is transmitted at a rate of more than twice that per program, different handling is required when receiving it. In other words, normally, in the case of single transmission using the vertical feed method, one column is transmitted for each field, but in the mixed method, the vertical feed method is transmitted once every N fields, so the transmission Sometimes, image signals for N columns are transmitted all at once. Hereinafter, the former will be referred to as the "vertical feeding [single] method," and the latter will be referred to as the "vertical feeding [mixed] method."
It is called ``Method''.

However, although various still image transmission methods have been proposed, conventional still image receiving devices have been unable to receive only one method. Furthermore, if one wishes to receive signals of two or more types of systems, it is necessary to separately provide a receiving apparatus for each system, which is inconvenient in that the apparatus becomes complicated and costs increase.

Therefore, in view of the above, the present invention provides a receiving device that can receive any still image signal with one device, and can display an easy-to-see still image when receiving any system. The purpose is to

To this end, in the present invention, a main memory having a storage capacity for the number of lines necessary to display a still image, and a main memory having a storage capacity for the number of lines required to display a still image, and a main memory having a storage capacity for the number of lines required to display a still image, and a main memory having a storage capacity for the number of lines required to display a still image, In order to temporarily store all image signals for one time, a buffer memory with a storage capacity equal to or greater than the number of bits of the superimposed image signal in the method with the largest number of bits is provided for each method. be equipped.

Then, it detects the system identification signal added to the superimposed still image signal and determines which system the received still image signal belongs to,
The buffer memory that stores the transmitted image signal for one time is shifted in advance by a predetermined number of bits required for each method according to its discrimination output and the specified input of the specified program, A still image can be displayed, and the image signal is transferred from the buffer memory to the common main memory using a transfer method suitable for each system, and is stored in a predetermined storage location.

In this way, regardless of which system still image signals are received, the image signals can be stored in a predetermined order in the main memory using the buffer memory and the common main memory. The receiver receives still image signals of all transmission methods.

Furthermore, the frequency of the display clock pulse for driving the main memory is switched according to the method discrimination output determined by detecting the method identification signal, so that the aspect ratio of a single image is almost constant regardless of which method is received. This feature is characterized in that it is controlled so that an image that is easy to see is always displayed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings showing a transmission system and a still image receiving apparatus according to an embodiment thereof.

First, details of the transmission method of still image signals received by the apparatus of this embodiment will be explained. In the following description, it is assumed that character information is transmitted as still image information.

First, FIG. 1 shows the principle of the lateral feed method. In this horizontal feed method, each character of multiple lines of character information to be transmitted, that is, one unit image, is 16 bits wide x 18 bits high, and the character image of one line is
It is divided into picture elements of 245 horizontal bits and 18 vertical bits as shown in 1.
Then, this is scanned in the horizontal direction starting from the uppermost line as indicated by the dashed dotted line, and an image signal of 245 bits per line is extracted as indicated by X2. The extracted image signal X2 is multiplexed line by line in one arbitrary horizontal period during the vertical retrace period of the television signal and sent out. Repeat this from the top line to the bottom line.

Figure 1 X4 and X5 show how a still image signal is superimposed on a television signal. However, the image signal X2 for one horizontal line of the still image is superimposed on the horizontal scanning period (hereinafter referred to as the 20th H). Along with this, a 2-bit method identification signal ID (“10” for the horizontal feed method) indicates that this image signal is of the horizontal feed method.
) and a 4-bit program code signal PC indicating which one of multiple types of programs, for example nine programs "a" to "i", this image signal belongs to.
, an 8-bit line number code signal LN indicating which horizontal line this image signal belongs to from the top of the still image, and each of these signals ID, PC,
A start signal STX indicating the reference phase of LN and X2 is added and transmitted in a superimposed manner.

In addition, when transmitting character information consisting of multiple lines (usually 8 lines), before transmitting a still image signal for one line, it is necessary to determine the line number of the subsequent image signal in the preceding field. Sends a line number code signal indicating the line number. As this line number code signal, a large number that is never used as a line number code signal is used, and in this case, a value of "11110001" or more is used, and the last four digits indicate the line number. In the field for transmitting this line number code signal, no image signal is superimposed, but the line number code signal is superimposed at the position of the line number code signal LN.

The receiving side receives such a still image signal, extracts only the image signal X2 of the desired program, stores it in the buffer memory, and transfers it to a predetermined line position in the main memory and stores it sequentially. A character image is read out by the display clock in synchronization with the scanning of the tube and displayed on the cathode ray tube as shown in X3. The solid line part in X3 is the image of the line that has already been received, the diagonal line part is the line that is being received, and the broken line part is the image of the line that will be received from now on. In the apparatus of the embodiment described later, a main memory with a storage capacity of two lines is used, so two lines of such character images are displayed on the cathode ray tube.

Next, FIG. 2 shows the principle of the vertical feeding (single) method. In the vertical feed method, the character image to be transmitted is
Each unit image is decomposed into picture elements of 16 bits horizontally x 16 bits vertically, and these are scanned vertically starting from the leftmost column as indicated by the dashed dotted line, and each column is divided into 16 bits per column as shown in Y2. extract the image signal. The extracted image signal Y2 for one column has two bits, separation bit SP and stop bit ST, added to the beginning to make a total of 18 bits, and one arbitrary horizontal line during the vertical retrace period of the television broadcast signal for each column. During this period, the data is multiplexed and transmitted at the 20th H. Repeat this for each column of the leftmost row. However, in this method, the image signals of five types of programs, for example "I" to "Ho", are transmitted in one horizontal period, and for this purpose, all character images of each program are decomposed into Y1. , the image signals extracted from the respective programs are arranged in chronological order in the order of programs "A" to "Ho" as shown in Y2, and are multiplexed within one horizontal period.

Y4 and Y5 indicate how a still image signal is superimposed on the television signal using this method, and in this case also a 2-bit start signal STX and a 2-bit method identification signal ID (“00” and “00” in the vertical feed method) are used. ) is added to the beginning and superimposed. However, in this vertical feed system, the arrangement order of the 18-bit image signals Y-i to Y-ho directly indicates the program, and therefore, no program code signal or line number code signal is used.

On the receiving side that receives still image signals of such a vertical feed [single] method, all image signals YI to YHO of five programs are temporarily stored in a buffer memory, and then the image signals of the desired program are transferred to this buffer memory. Shift the image signal in advance until it is output to the output terminal of the buffer, roll the storage position in the main memory to the left one bit at a time, and always transfer and store the image signal for one column from the buffer memory to the storage position of the last column. do. Then, a character image is read out from this main memory in synchronization with the scanning of the cathode ray tube and displayed on the cathode ray tube as shown in Y3. The solid line portion in Y3 is the image of the column that has already been received, the diagonal line portion is the image of the column that is currently being received, and the broken line portion is the image of the column that will be received from now on. At this time, the image signal is transferred to the last row while rolling the storage location in the main memory to the left, so the displayed character image is displayed while rolling to the left like a lightning news, and new characters are displayed from the right end. It will appear.

In this way, when receiving data using the vertical feed method, the character image is rolled to the left on the cathode ray tube, making it extremely difficult to see if it is displayed in two lines. When receiving a message, only one line is displayed to make it easier to understand.

Finally, FIG. 3 shows the transmission mode in the mixed system. Since this method is a mixture of the above-mentioned horizontal feed method and vertical feed method, the image signals of each are basically the same as those described above, but changes have been made to allow for the mixture. .
In other words, in this method, as shown in Z1, the still image signal X' of the horizontal feed method is superimposed on three consecutive fields, and the still image signal Y' of the vertical feed (mixed) method is superimposed on the next field. The vertical feed method is added to every 4 fields so as to be superimposed on the field. In order to prevent the transmission speed from changing even if the still image signal Y' of the vertical feed (mixing) method is distributed once every four fields, as shown in Z3 and Z4,
For the still image signal Y' of the vertical feed [mixing] method that is multiplexed at the 20th H, a total of 72 bits of image signals for 4 columns are superimposed at one time, and instead the number of programs is divided into α, β, and γ programs. It has been reduced to three types. In this way, on the receiving side, the image signals for these four columns are temporarily stored in the buffer memory, and then transferred to the main memory at a rate of one column for each field, as explained in Fig. 2 above. Display can be made in exactly the same way as in the case of the vertical feed [single] method. The still image signal X′ of the horizontal feed method is Z1
As shown in FIG. 1, it is exactly the same as that shown in FIG.
Therefore, in this horizontal feed method, still images can be received and displayed in exactly the same manner as in the case of FIG. However, in this horizontal feed method, the first
Although the transmission speed is reduced to three-fourths of that in the case shown in the figure, the transmission speed can be maintained by reducing the number of programs.

In this mixed method as well, a 2-bit start signal STX and a 2-bit method identification signal ID (for the horizontal feed [mixed] method, it is set to ``10'', which is the same as in the case of the horizontal feed method shown in Figure 1), and for the vertical feed [mixed] method, In this method, "01" is added to the beginning of the data to distinguish it from the vertical feed method shown in FIG. 2, and the data is superimposed.

In any of the methods explained above in Figures 1 to 3, all signals are either "1" or "0".
Transmit as a value signal. In addition, in each method, the clock frequency for transmission is 8/8 of the color subcarrier frequency sc.
5 times (5.73MHz) and synchronized with the color subcarrier of the television signal to be multiplexed. This is to facilitate the sampling operation of each signal on the receiving side.

Next, an embodiment of a receiving device that can easily receive all of these three types of still image signals will be described with reference to FIGS. 4 to 7.

First, FIG. 4 shows the schematic structure in a block diagram.

In the figure, 1 is a receiving circuit that includes a tuner, a VIF circuit, a video detection circuit, etc., and receives a television signal on which a still image signal is multiplexed at the 20th H during the vertical retrace period, and 2 is a receiving circuit that receives the received still image signal. A waveform shaping circuit slices the image signal to form a waveform into a binary signal, and 3 is a sampling gate circuit that extracts only the portion of the still image signal multiplexed at the 20th H.

A buffer memory 4 temporarily stores at least an image signal portion of one received still image signal. This buffer memory 4 needs to be set to have a capacity that can store all the image signals sent at the 20th H, regardless of which system the received still image signals are of. Here, since the image signal X2 in the horizontal feed method is 245 bits, which is the most common, a larger, general-purpose signal of 256 bits is used.

Furthermore, a main memory 5 transfers the image signals of the desired program among the received still image signals from the buffer memory 4 and accumulates and stores them in a predetermined order suitable for display. This main memory 5 must store all image signals of character images to be displayed on the cathode ray tube, and in this embodiment, the display image consists of 1 line of 18 lines, and this is displayed in 2 lines. Therefore, I use one with a storage capacity of 256 x 36 bits. As this memory 5, a shift register or the like is suitable.

When displaying a character image, the image signal is read out from the main memory 5 using the display clock pulse, and the display gate 6 outputs all two lines when receiving the horizontal feed method, and outputs only one line when receiving the vertical feed method. . The mixed amplification circuit 7 then mixes the signal with a normal television broadcast video signal and applies it to the cathode ray tube 8, thereby superimposing and displaying the received character image on the screen. Here, as mentioned above, two lines of character images can be displayed, the upper line is the 203rd to 220th line, and the lower line is the 229th to 229th line.
At the 246th hour, there will be 18 lines each.

FIG. 5 shows the display state, where X is when a still image is being received by the horizontal feed method, and Y is when a still image is being received by the vertical feed method. In either case, the main memory stores at least the display period of the upper row of the 203rd to 220th H,
The display period of the lower row from 229th to 246th H is clocked by a display clock pulse, and when receiving the horizontal feed method, both the upper row image signal and the lower row image signal are read out and displayed in two lines. . On the other hand, when receiving the vertical feed method, only the image signals in the lower row of the 231st to 246th H are read out and only the lower row is displayed in order to make it easier to see as described above. However, in this case, in the vertical feed method, the vertical direction of the character image is 16 bits, so the 229th and 230th lines are not read out, and the 231st to 230th lines are read out.
The image signal is read out during 16H of the 246thH.

Next, in FIG. 4, a description will be given of the parts that control the above-mentioned parts. First, 9 is a synchronous deflection circuit that generates horizontal pulses and vertical pulses synchronized with the horizontal and vertical synchronous signals of the received television signal. Based on the horizontal and vertical pulses obtained here, the sampling pulse generation circuit 10 generates a sampling pulse at the 20th H during the vertical retrace period of each field, and opens the sampling gate circuit 3 to generate a sampling pulse at the 20th H.
Only the still image signal multiplexed to the eye is extracted. The extracted still image signal is added to the buffer memory 4, as well as to the start detection circuit 11, system discrimination circuit 12, program detection circuit 13, and line code detection circuit 14.

The system discrimination circuit 12 is as shown in FIG.
A 2-bit latch circuit 30 is provided to retrieve and store the system identification signal ID using the sampling clock pulse. And gates 31X, 31Y, 31
When the method identification signal ID is "10", the gate 31X outputs an output indicating the horizontal feed method, and when the method identification signal ID is "00", the gate 31Y outputs an output indicating the vertical feed [single] method. The output that shows that
Vertical feed from gate 31Y′ when “01” [mixed]
Each generates an output indicating that it is a method. The gate 32 generates an output during the vertical feed method.

15 is a display clock generation circuit that generates display clock pulses for driving the main memory 5. The display clock generation circuit 15 controls a gated oscillator with a signal that is a delayed horizontal pulse, and is delayed by a predetermined time from the horizontal synchronizing signal. A display clock pulse of about 6 MHz is generated from the point in time (corresponding to the left edge position of the displayed image).

Since the number of vertical and horizontal bits of a unit image differs depending on the format, the frequency of the display clock pulse generated here is determined by the format of the format discriminating circuit 12 so that the image can be displayed with approximately the same aspect ratio no matter which format is received. Switch depending on the discrimination output.

On the other hand, 16 is a sampling clock generation circuit that generates a sampling clock pulse for extracting the sent still image signal and storing it in the buffer memory 4, and a color subcarrier generation circuit 17.
The color subcarrier sc created in step 1 is multiplied and frequency-divided to generate a sampling clock pulse having the same frequency of 8/5 sc as the still image signal and phase-locked to the start signal STX. These two clock pulses, the display clock pulse and the sampling clock pulse, are added to the clock counter 18.

This clock counter 18 is for counting and generating clock pulses of 256 bits every H. The operation has two stages. First, at the 20th H when the still image signal is being transmitted, the clock pulses from the sampling clock generation circuit 16 are counted and the 256-bit clock pulses are counted to store the image signal in the buffer memory 4. Generates sampling clock pulse. The timing at which the sampling clock pulse starts to be generated is controlled by a sampling start control circuit 19. In other words, when the method determining circuit 12 determines that the received signal is of the horizontal feed method, the start signal is
The sampling clock pulse is generated from the time when the image signal starts 14 bits after the end of STX, and if it is determined that the vertical feed type is used, the sampling clock pulse is generated 2 bits after the end of the start signal STX. The sampling clock pulse is controlled to be generated from the time when the image signal starts after the lapse of .

By applying this sampling clock pulse to the buffer memory 4 via the buffer memory clock circuit 20, the image signal is transferred to the buffer memory 4.
Write it down and memorize it. As mentioned above, the buffer memory 4 has a storage capacity of 256 bits, so after adding 256 bits of this sampling clock pulse, no matter which method is used, one image multiplexed in the 20th H is stored. All signals are stored, and the most advanced bit signal appears at the output terminal.

The input control circuit 21 controls the opening and closing of the buffer memory clock circuit 20, and is operated by the viewer from the program designation circuit 22 while receiving television signals multiplexed in a mixed method. α of the vertical feed [mixing] method,
If it is specified to receive either the β or γ program, the system determining circuit 1 determines that the still image signal X' of the vertical feed (mixed) system has been received.
2, the buffer memory clock circuit 20 is opened and a sampling clock pulse is applied to the buffer memory 4 to store the image signal. When receiving this vertical feed [mixing] method, as mentioned above, the image signals for 4 columns sent at the 20th H of a certain field are transferred to 1 column between that field and the following 3 fields. Since the image signals are transferred to the main memory 5 minute by minute, it is necessary to leave untransferred image signals in the buffer memory 4 at least during that time.
This is to prevent sampling pulses from being applied to the buffer memory 4 and not being written into the buffer memory 4 even if Y' is being sent. For this purpose, an input inhibit pulse is generated. When receiving a method other than this, a sampling pulse is applied to the buffer memory 4 at the 20th H of each field to store the image signal.

As described above, it was possible to store the image signals in the transmitted still image signals in the buffer memory 4 each time, so next, among these image signals, only those of the program that you wish to receive can be stored according to each method. It is necessary to transfer the data to the main memory 5 using the same method. In the illustrated embodiment, when the main memory 5 is clocked for display, the image signal is transferred at a predetermined timing during the clocking.

Therefore, first, the portion of driving the main memory 5 with a display clock pulse for display will be explained. The display clock pulse generation circuit 15 is the 17th
Something like the one shown in the figure, about 6MHz as mentioned above.
Generates display clock pulses. This display clock pulse circuit 15 includes a gated oscillator 35 made up of gates 33 and 34, and its operation is controlled by a signal that is a delayed horizontal pulse, so that the display clock pulse is generated from a predetermined time delay from the horizontal pulse. to start. Since this generation start point corresponds to the left end of the character image displayed on the screen of the cathode ray tube 8, it may be determined as appropriate so that the character image can be displayed in the center.

Then, when it is determined from the gate 32 of the method determining circuit 12 that the vertical feed method is being received, the determination output is applied to the variable capacitance diode 37 via the resistor 36, and is controlled to increase the oscillation frequency, thereby increasing the period of the display clock pulse. control is made so that the aspect ratio of one unit image of a still image to be displayed is always kept almost constant, regardless of whether it is received in the vertical feed method or in the horizontal feed method. In this way, it is possible to provide the same and easy-to-understand display regardless of which type of still image signal is received.

Note that instead of controlling the oscillation frequency to be high during vertical feed mode reception, the oscillation frequency may be controlled to be low during horizontal feed mode reception.

Needless to say, the control ratio of the oscillation frequency is appropriately determined depending on the mode of transmission.

Then, in the clock counter 18, the above-mentioned
The display clock pulses are counted during other periods except the 20th H, and 256 bits are output every H, and added to the main memory clock circuit 23.

On the other hand, 24 is a line counter that counts horizontal pulses supplied from the synchronous deflection circuit 9 and generates an output. The counting method is as follows:
Counting starts from the 21st hour and repeats every 26 hours. This 26H period is the display division for one line when displaying a character image, of which the front 18H period is the display part of the character image and the remaining 8H
Use period as interline space. When displaying a vertically-adjusted character image, since one column is 16 bits, the first 2H period is used as a space, and the 16H period is used as a display portion. If you start counting from the 21st H to the 26th H as one line, you can obtain a display section of 8 lines on the effective part of the cathode ray tube 8. Use rows for display. Therefore, the 203rd to 220th lines become the display part of the 7th line (hereinafter referred to as the upper line), and the 229th line becomes the display part of the 7th line (hereinafter referred to as the upper line).
The 8th line (hereinafter referred to as the lower line) is displayed from 246th H to 246th.

Therefore, the row pulse generation circuit 25 counts the output of the line counter 24 and generates row pulses during the period between the upper row display portion and the lower row display portion. The row pulses of both the upper row and the lower row are taken out for 18H periods and applied to the main memory clock circuit 23, and display clock pulses are applied to the main memory 5 for the entire period of the display portion for two rows to drive it. The main memory 5 is driven in exactly the same way both when receiving data using the horizontal feed method and when receiving data using the vertical feed method.

When receiving the horizontal feed method, row pulses for two rows of 18H periods each for the upper row and lower row are applied to the display gate circuit 6, and the row pulses for the upper row and lower row are
Take out the image signals for the rows and divide them into 2 as shown in Figure 5.
Display a line of text images. On the other hand, when receiving the vertical feed method, the upper 2H period of the lower row is excluded.
A row pulse of 16H period is applied to the display gate circuit 6, an image signal for one row is taken out from the main memory 5, and a character image of one row is displayed as shown in FIG. 5Y. In this way, main memory 5 is driven by display clock pulses.

Next, a portion of transferring the image signal from the buffer memory 4 to the main memory 5 will be explained. First, transfer during reception using the horizontal feed method will be explained. As mentioned above, when a horizontal feed still image signal is received at the 20th H, the image signal for one line is sent back to the buffer memory 4 from its output terminal.
Since it is stored in 245 bits, when transferring, it is necessary to check whether the image signal belongs to the group desired to be received, whether it is from the upper row or the lower row, and whether the image signal is from the upper row or the lower row. It detects which line from the top it is, and also detects which storage location of the main memory 5 is currently being driven (is it ready for input/output), and then When the storage position of the line to which the image signal corresponds in the memory 5 is being driven, the image signal may be transferred from the buffer memory 4 to the main memory 5, and a new image signal may be written in the line.

Therefore, first, the row code detection circuit 14 extracts and identifies the row code signal added to the still image signal, and determines whether the image signal being sent is from an odd numbered row or an even numbered row. Detect. Here, the odd numbered rows are displayed in the upper row and the even numbered rows are displayed in the lower row.
When it is detected that the still image signal of the odd numbered row has been sent, the row pulse generation circuit 25 generates a row pulse for the display portion of the upper row, and it is detected that the still image signal of the even numbered row has been sent. When this occurs, a row pulse is generated for the display portion of the lower row, which is added to the transfer control circuit 26 to enable transfer.

On the other hand, the program detection circuit 13 extracts the program code signal PC added to the sent still image signal, and the program specification circuit 22 compares it with the program desired to be received specified by the viewer's operation. Then, when the two match, that is, when a still image signal of the program desired to be received is sent, a program match output is generated. 27 is an X transfer pulse generation circuit, which counts vertical pulses when a program matching output is generated and a still image signal of the desired program is being sent, and transfers the image signal at that time from the top of the row. It detects what line it is, and compares it with the count output of the line counter 24, and when the two match, that is, the line of the sent still image signal and the line being driven in the main memory 5. When they match, an X transfer pulse with a width of 1H period is generated. Since a line number code signal LN is added to the still image signal of the horizontal feed method, it may be detected, but in this horizontal feed method, after the line code signal is sent, one line per field is Since the image signal is transmitted one by one, it is possible to easily detect which line the image signal belongs to by counting the number of fields in which the programs match.

Then, in the transfer control circuit 26, when a row pulse indicating an upper row or a lower row and an X transfer pulse indicating line coincidence are applied, the main memory 5
The input circuit of the main memory 5 is switched so as to apply the output signal of the buffer memory 4 to the input terminal of the main memory 5, and at this time, the buffer memory clock circuit 20 applies the same display clock pulse as the main memory 5 to the buffer memory 4 to drive it. A 245-bit image signal is read from the buffer memory 4, and the image signal for one line is transferred and written to the storage location of that line in the main memory 5. By repeating this transfer operation each time a still image signal of a desired program is sent, new image signals can be stored one after another in the storage position of a predetermined line in the main memory 5. It is possible to receive a moving still image signal and display it in two lines as shown in FIG. 5X.

Next, a description will be given of the transfer operation when receiving data using the vertical feed method. In this vertical feed method, as mentioned above, the program code signal is not added, and the arrangement order of the image signals directly indicates the type of program, so the one-time image sent at the 20th H When signals are stored in the buffer memory 4, the image signals of the earliest program (i.e. program A or program α) are stored in order from the output terminal, and the image signal of the program desired to be received does not necessarily appear at the output terminal. Must not be. Therefore, when receiving this vertical feed method, before transferring the image signal from the buffer memory 4 to the main memory 5, the storage position of the buffer memory 4 is shifted in advance according to the program desired to be received. Make sure that the leading edge of the image signal appears at the output terminal.

For this reason, this device is provided with a shift control circuit 28 to perform shift control prior to transfer. That is, this shift control circuit 2
8 is a system determination circuit 1 which determines which program the program designation circuit 22 desires to receive.
The still image signal sent in step 2 is sent vertically [single]
The number of bits to be shifted is determined based on whether the shift type is a vertical feed type or a vertical feed (mixed) type. A display clock pulse is outputted by the buffer memory 4, and the display clock pulse is added to the buffer memory 4 to shift its storage position.

For example, in the case of receiving a vertical feed (single) system H program, if a still image signal as shown in FIG. 2 Y4 is received in the 20th H and the 90-bit image signal is stored in the buffer memory 4, The beginning of the image signal Y of the first program A, that is, SP, is delivered to its output terminal. Therefore, in this case, for example, the 21st H after receiving the still image signal at the 20th H.
Apply a clock pulse to the buffer memory 4 and shift it by a total of 361 bits for the A and B programs that precede the C program so that the leading edge of the image signal YC of the C program appears at the output terminal of the buffer memory 4. .

In addition, when receiving a γ program in the vertical feed (mixed) format, if a still image signal such as Z3 in Figure 3 is received in the 20th H and the 216-bit image signal is stored, the output terminal will be The beginning of the image signal Yα of the first α program, that is, the SP has arrived. Therefore, in this case, α before the γ program in the 21st H,
Buffer memory 4 for a total of 144 bits for the β program
A clock pulse is applied to and shifted so that the leading edge of the image signal Yγ of the γ program appears at the output terminal of the buffer memory 4.

In this way, by making the image signal of the program that you wish to receive appear at the output terminal of the buffer memory 4, the image signal is sent to the end of the main memory 5 as described below at the time of the display clock of the main memory 5. can be transferred and stored in the queue, and program selections can be made.

In this vertical feed method, as described above, an image signal obtained by scanning a character image in the vertical direction is sent, so from buffer memory 4 to main memory 5
1 in the vertical direction in the main memory 5.
Although it is necessary to transfer data to a memory location corresponding to one column, it is always transferred to the memory location in the last column of the main memory 5, and prior to transferring one column, the previous data in the main memory 5 is By shifting the storage position of the image signal to the left by 1 bit per field, it is possible to add new rows of images one after another from the right end while rolling the character image to the left. As shown in Figure Y, it is possible to display character images that roll like lightning news.

Reference numeral 29 denotes a Y transfer pulse generation circuit for performing such a transfer operation, and the Y transfer pulse generation circuit 29 generates a Y transfer pulse for each line in the main memory 5 based on the display clock pulse from the clock counter 18 and its count output.
A 1-bit width Y transfer pulse is generated at the 256th bit clock, that is, at the last column clock.
Then, this is added to the transfer control circuit 26, and when the method discrimination circuit 12 is generating a detection output that detects the vertical feed method, and when the row pulse generation circuit 25
When a row pulse for the lower row is being generated, the 1-bit image signal of that line is transferred from the buffer memory 4 to the input terminal of the main memory 5 at the 256th bit of each line and stored therein. No.
When the transfer of one bit worth of image signal is completed at the 256th bit, a one bit shift pulse is then applied to the buffer memory 4 to shift it by one bit in preparation for transfer on the next line. However, the first
At the 229th H, the first signal of the image signal for one column has already appeared at the output terminal of the buffer memory 4 due to the storage in the buffer memory 4 at the 20th H and the shift control at the 21st H, so this 1-bit No shifts will be made. This transfer operation is repeated from the 229th H to the 246th H, which are the display portions in the lower row, and the image signals for one column are stored in the storage position of the last column of the main memory 5. In this way, this device can share the buffer memory 4, main memory 5, and most other circuits, and can receive still image signals of all transmission methods with an extremely simple configuration.

It should be noted that various types of circuit systems may be used in addition to the above-described embodiments to enable reception of signals of any of these systems.

As described in detail above, the still image receiving device of the present invention can receive still image signals of any of the horizontal feed method, vertical feed [single] method, vertical feed [mixed] method, etc. Since the image signals are temporarily stored in the buffer memory and then transferred to the common main memory in a predetermined order based on the system discrimination output and the program specification input, the buffer memory, main memory, transfer control circuit, and clock It has a simple configuration that uses all related circuits in common, and can receive all signals using either method. Furthermore, since the frequency of the display clock pulse is controlled according to the method, an easy-to-read display with approximately the same aspect ratio can be produced regardless of the method used.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are schematic diagrams and waveform diagrams for explaining the transmission method of still image signals received by the still image receiving device of the present invention, and FIG. FIG. 5 is a front view showing the mode of displaying still images by the still image receiving device, and FIGS. 6 and 7 are detailed circuit diagrams of the main parts of the device. 1... Receiving circuit, 2... Waveform shaping circuit, 3...
Extraction gate circuit, 4... Buffer memory, 5...
Main memory, 6...Display gate circuit, 7...Mixing amplifier circuit, 8...Cathode ray tube, 9...Synchronized deflection circuit, 10...Sampling pulse generation circuit, 11...Start detection circuit, 12...Method discrimination Circuit, 13...
Program detection circuit, 14...Line code detection circuit, 15
... Display clock generation circuit, 16 ... Sampling clock generation circuit, 17 ... Color subcarrier generation circuit, 18 ... Clock counter, 19 ... Sampling start control circuit, 20 ... Buffer memory clock circuit, 21...Input control circuit, 22...Program specification circuit, 23...Main memory clock circuit, 24...Line counter, 25...Line pulse generation circuit, 26...Transfer control circuit, 27...Transfer pulse generation Circuit, 28...Shift control circuit, 29
...Y transfer pulse generation circuit.

Claims (1)

[Claims] 1 At least one of still image signals of multiple types in which each unit image of a still image is separated and scanned in the vertical and horizontal directions with different numbers of bits.
a receiving circuit that receives television signals multiplexed during a horizontal scanning period during a vertical retrace period;
It has a buffer memory capable of storing image signals multiplexed within the horizontal scanning period, regardless of the format, and a storage capacity capable of storing all image signals of still images to be displayed. a main memory; a system determination circuit that determines which system the received still image signal belongs to; and a system determination circuit that determines which system the received still image signal is of; A transfer control circuit that transfers the data to a predetermined storage device in the memory and stores it, and switches the frequency of the display clock pulse for the main memory according to the method discrimination output, and displays still images of either method with approximately the same aspect ratio. What is claimed is: 1. A still image receiving device characterized by comprising: switching means for switching.