JPS6118041A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To decrease the number of steps of a microinstruction by selecting the microinstruction or the output of an arithmetic processing signal generating circuit by the microinstruction itself and giving the arithmetic designation to an arithmetic circuit from the result of said selection. CONSTITUTION:A ROM10 stores the arithmetic designation information containing the arithmetic type of an instruction and the arithmetic data width according to an instruction code. An arithmetic processing signal generating circuit 11 selects a microinstruction or the circuit 10 according to the contents of said microinstruction. Based on the result of this selection, the arithmetic is designated to arithmetic circuits 12 and 13. Thus several types of instructions can be processed in the addresses of the same microprogram. This attains reduction of the number of steps of a microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic processing device in a data processing device using a microprogram control method.

(Conventional technology) An example of a conventional arithmetic processing device is shown in FIG.

In FIG. 12, numeral 1.2 is an 8-bit arithmetic circuit having the same configuration, and arithmetic circuits 1 and 2 constitute an 18-bit arithmetic device. 3 is a carry look-ahead circuit to the arithmetic circuit l, PB
A and PBB are input buses, and RBS is an output bus.

FIG. 13 is a detailed diagram of the arithmetic circuit 1 or 2 in FIG. 12, where 4 is an arithmetic and logic operation circuit, 5 is an input/output signal control circuit for the arithmetic and logic operation circuit 4, and 6 is a fixation for performing lO base operation. A pattern generation circuit, 7 is a circuit for sending an operation signal to the arithmetic logic operation circuit 4 in accordance with an operation designation signal sent from a predetermined field of the microinstruction, 8 is a register for latching the operation result of the arithmetic logic operation circuit 4, A and B. is PB in Figure 12
A, input data from PBB, RBS is R in Figure 12
It is the same as BS, and BiS is a byte position identification signal that determines the control method of the control circuit 5. FIG. 14 is a detailed diagram of the control circuit 5. The meanings of the signals in FIG. 14 are as follows.

1) LB---- LATCH least significant bit signal 2
) SG------A, B input's most significant bit match signal 3) P------A, B input generated propagation carry signal 4) CF------A , B input calculation result carry signal 5) G---1---A, B input generation carry signal 6) MB-1---LATCH least significant bit signal?
)3CO---3-2 conversion carrier output signal 8)
3C1---3-2 conversion carrier single power signal 9) BiS-
--Byte position identification signal BiS in FIG. 14 is the same signal as BiS in FIG. 2, and the "l" signal is input to the arithmetic circuit l in FIG. As a result, the signal shown in FIG. 15 can be used as a signal with a different meaning.In this embodiment, the signal is sent from the arithmetic circuit 1 or as a signal representing the state of the arithmetic result. 12th
The case where the arithmetic processing unit shown in the figure performs the byte unit addition operation “00F 0 (H1 + O007(H)”) will be explained as an example. In this embodiment, the operation processed by the arithmetic unit and the operation rtJ are microinstructions. In the processing device shown in FIG.
If it is sent to A, PBB-H and added in arithmetic circuit 1.2, "OOF 7 (H)" is sent as an operation on RBS, and "F7 (H)" is obtained as a byte unit operation. . Here, the state signals (N, Z.

C) is processed as follows.

1) N-----When the most significant bit of the latch is 1
0 when the most significant bit of the latch is 0 2) Z---m-When the latch output is O 0 when the latch output is other than 0 3) C---1--When a carry occurs as a result of an operation 1
When a carry does not occur as a result of an operation (problem to be solved by the invention) In the byte unit addition operation described above, a correct result is obtained in byte units, but the state signal (N, Z, C) of the operation result is is obtained from the arithmetic circuit l except for the Z signal, and its value is (0, 0, 0), so a correct status signal cannot be obtained. In order to obtain a correct status signal in the arithmetic processing device shown in FIG. The data is sign-extended and each “
F F F 0 (H)”.

If you perform the addition after setting 0007(-), it becomes “F
F F 7. The correct value (1, 0, 0) can be obtained as a state signal.However, the data must be sign-extended before execution of the operation, which reduces processing power and requires a circuit to perform sign-extension. Become.

Word unit addition operation “0OFO(H)+0007(H
)', the addition can be performed without sign extending the input data, and the operation result is "00 F 7
(H,”), (0, 0, 0) is correctly obtained as the status signal. However, in this case, the operation width is specified by the microinstruction, so the byte operation and word operation of addition are performed in different microinstruction steps. The same is true for processing the byte and word operations of subtraction.Furthermore, since the operations are specified in microinstructions, addition and subtraction must be processed in different microinstruction steps. First, it is not possible to reduce the number of microinstruction steps.

Accordingly, it is an object of the present invention to commonly instruct operations of each instruction using microinstructions, thereby reducing the number of microinstruction steps.

(Means for Solving the Problem) The present invention provides a read-only memory (ROM) that stores operation type specification information and operation data width specification information, and stores the operation type and operation data width from the read-only storage according to an instruction code. It is characterized by instructing the execution of operations using reading and microinstructions.

(Function) According to the present invention, the operation specification of the arithmetic circuit is the operation type and operation width from the read-only storage device or the microinstruction itself, and which one is selected is determined according to the microinstruction.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which 10 is a read-only storage device (hereinafter abbreviated as MCC) in which control information of instructions executable by a data processing device is stored, and 11 is an arithmetic operation device. Processed signal generation circuit 12 and 13 are arithmetic circuits having the same configuration as arithmetic circuit 1.2 shown in FIG. 12, 14 and i
5 is a 16-bit register, 18 is a status signal selection circuit, 17 is a status signal set circuit, 19 is an instruction information signal line that sends an instruction code that specifies the operation and operation width of MCCl0, and 20 is an operation processing signal generation circuit from MCCIG. 21 is a signal line for an arithmetic width designation signal sent from MCCl0 to the arithmetic processing signal generation circuit 11; 22 is a signal line for an arithmetic processing signal generation circuit 11 from a predetermined field of the microinstruction; 23 is a signal line for an operation width designation signal sent from a predetermined field of the microinstruction to the operation processing signal generation circuit 11; 24 is a signal line for an operation width specification signal sent from the operation processing signal generation circuit 11 to the operation circuit 12; and 13, signal lines 25 and 26 are signal lines for byte position identification signals sent from the arithmetic processing signal generation circuit 11 to the arithmetic circuits 12 and 13, and 27 and 28 are arithmetic processing signal generation circuits. A signal line 29 is a signal line for a write instruction signal sent from ll to registers 4 and +5, a signal line 29 is a signal line for a state signal selection signal sent from the arithmetic processing signal generation circuit 11 to a state signal selection circuit f6, and PBA and PBB are shown in FIG. RBS is the same input bus as shown in Figure 12, and RBS is the same output bus as shown in Figure 12. The fields for the calculation and calculation width are shown below.The meaning of each field is as follows.

1) LF------Operation width specification field in MCC 2) IF------Operation specification field in MCC 3) DTP---Operation width specification field in microinstruction 4) ALF-m- Operation designation fields in microinstructions and the characteristics of each field are shown in FIGS. 3 to 6. EXT in Figures 5 and 6 has an operation and operation width of MC.
This is the order of microinstructions indicated by the LF and IF fields in one entry of control information stored in Cl0.

FIG. 7 shows the characteristics of the arithmetic signal sent from the arithmetic processing signal generation circuit 11 to the arithmetic circuits 12 and 13. FIG.
FIG. 9 shows the characteristics of the byte position identification signal sent to the registers 14 and 1 from the arithmetic processing signal generation circuit 11.
5 shows the characteristics of the write instruction signal sent to No. 5. 1st O
The figure shows the characteristics of the state signal selection signal sent from the arithmetic processing signal circuit 11 to the state signal selection circuit 16. FIG. 11 shows the input/output characteristics of the arithmetic circuit according to the characteristics of the byte position identification signal. Below, as operation examples, processing of addition byte operations and word operations, and subtraction byte operations and word operations will be described.

Now, with the contents of address 100 (H,) of the microprogram,
Perform the calculations in registers 4 and 5 and store the result in register 14, and the calculation and calculation width are "
Suppose that it is indicated that "EXT" is specified.

It is also assumed that the microprogram execution start address for addition byte operations and word operations, and subtraction byte operations and word operations are all at address 100(H). Also, as data, the register 14 contains "' OOF 0 (H
)'", and the register 15 stores "000ha8)".

First, the calculation and calculation width processing operations by the calculation processing signal generation circuit 11 are performed. At the start of instruction execution, the LF of the entry corresponding to the instruction code in the control information stored in the MCC 10
, IF contents are sent to the arithmetic processing signal generation circuit 11. The contents of LF and IF are shown below.

l) Byte operation of addition---LF=0 (punishment.

IF=O, River 2) Word operation of addition---L F = 1 (1
1).

IF=O(,4) 3) Subtraction byte operation---L F = 0(H)
.

IF ” 1 (H) 4) Word operation of subtraction---L F = l (H
).

IF=1cH) From the microinstruction at address 100(,), DTP="E
XT", ALF="EXT" signals are sent to the arithmetic processing signal creation circuit 11. In the arithmetic processing circuit creation circuit 11, DTP=" from the microinstruction at address 100tH).
When the signals ``EX T'' and ALF="EXT'' are received, LF and IF sent from MCCl0 are selected as signals specifying the calculation and calculation width. Next, according to the control signal sent from the calculation processing signal generation circuit 11. Arithmetic circuits 12 and 13. Registers 14 and 15. Status signal selection circuit I
An example of operation of B is shown below.

1) In the case of addition byte operation "0 (H)" is sent from the arithmetic processing signal generating circuit 11 to the arithmetic circuits 12 and 13 as an arithmetic processing signal (see FIG. 7). "l (H)" is sent to the arithmetic circuit 13 as a byte position identification signal, and no significant signal is sent to the arithmetic circuit 12 (see FIG. 8).
There is no sign extension on PBB゛” OOF o,
, , +1, and "0007 (H,") are sent out.The arithmetic circuit 13 receives data "FO(+-+1") from the input buses PBA and PBB in the lower 8 bits, respectively.
, input the data of "07(H)" and perform addition,
As the calculation result, "F7.H)" is sent onto the output bus RBS. Since “1°” is sent to the arithmetic circuit 13 as a byte position identification signal, the signal sent from the arithmetic circuit 13 to the status signal selection circuit 18 is “F 0 (H
)+07(H)''' resultant state signal (
N, Z, C). The arithmetic circuit 12 is an input bus PBA
, PBB to N1001.41” 1 “00(1)”
However, since no significant byte position identification signal is sent, the operation result sent to the output bus RBS is unpredictable, and the signal sent to the status signal selection circuit 1B is is also unpredictable.

'0' from the arithmetic processing signal generation circuit 11 to the register 14,
A write instruction signal of “l” is sent to the register 15,
The lower one byte "F7(H)" of the addition result of "OOF O(H)" and 00007(, )" is written to the register 15, and nothing is written to the register 14 (see FIG. 13).

A state signal selection signal "0" is sent from the arithmetic processing signal generation circuit 11 to the state signal selection circuit 1B, and the signal sent from the arithmetic circuit 13 to the state signal selection circuit 18 is selected as a state signal and sent to the state signal set circuit 17. sent (first
(See Figure 4).

11) In the case of word operation of addition, "0 (H>") is sent from the arithmetic processing signal generation circuit 11 to the arithmetic circuits 12 and 13 as an arithmetic signal (see FIG. 7), and as a byte position identification signal, the arithmetic circuit 12 “
1", "O" is sent to the arithmetic circuit 13 (see Fig. 8), "Q OF O (+
4)", "OO07,-" data are being sent.

The arithmetic circuit 13 connects input buses PBA and PBB to FO(H
)″, N07(,4)” are input and added, and “F7(,)” is output as the calculation result to the bus RBS.
Send upward. The arithmetic circuit 13 receives a byte position identification signal “
0'' is sent, the signal sent to the status signal selection circuit 2B does not represent the status signal (N, Z, C) (see Figure 11).The arithmetic circuit 12 is connected to the input bus PBA. , from PBB “
o o, H,", "00←)" is input from the arithmetic circuit 13 with the carry signal of the result of adding "FO(Ml" and "0η□)", and the addition is performed, and the calculation result is "00(1)" is sent onto the output bus RBS.Since the byte position identification signal "1" is sent to the arithmetic circuit 12, the signal sent to the state signal selection circuit to is the state signal (N, Z , C) (see Figure 11).

From the arithmetic processing signal generation circuit 11 to registers 14 and 15
A write instruction signal of “N1” and “1” (see FIG. 9) is sent to the register 15, and “OOF 0(H)+000” is sent to the register 15.
The lower 1 byte “F7(H)” of the operation result of “7LH)” is written, and the upper 1 byte “” o o
(,)” is written.

Arithmetic processing signal creation circuit! A state signal selection signal "1" is sent from 1 to the state signal selection circuit 1B (see FIG. 1O),
A signal sent from the arithmetic circuit 12 to the state signal selection circuit 1B is selected as a state signal and sent to the state signal set circuit 17.

11;) In the case of a subtraction byte operation, "1.H)" is sent from the arithmetic processing signal generation circuit 11 to the arithmetic circuits 12 and 13 as an arithmetic processing signal (see FIG. 7). From the arithmetic processing signal selection circuit 11 to the arithmetic circuits 12 and 13. Registers 14 and 15. The meaning of the signal sent to the status signal selection circuit 1B is the same as in case i).

jv) In the case of a subtraction word operation, "lfH" is sent from the arithmetic processing signal generation circuit 11 to the arithmetic circuits 12 and 13 as an arithmetic signal (see FIG. 7). 13. Register 14 and 15. Status signal selection circuit 1
The meaning of the signal sent to 6 is the same as in 11).

(Effects of the Invention) As described above, in the embodiment of the present invention shown in FIG. As a result of making it possible to arbitrarily specify the operation specification information and operation width specification information in the order of microinstructions, it is possible to process several types of instructions at the same microprogram address, thereby reducing the number of steps in the microprogram. Furthermore, the arithmetic processing signal generation circuit 11 to the arithmetic circuit 12
and 13 the byte position identification signal shown in FIG.

By sending the status signal selection signal shown in Fig. 1θ to the status signal selection circuit 16, byte operations can be processed without sign extension in a 16-bit arithmetic processing unit, and there is no need for a circuit for sign extension. It has a positive effect.

According to the present invention, various instruction operations of different operation types and different operation data widths can be executed with one microinstruction, and the number of microinstruction steps can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The field configuration diagram of the operation specification information and operation width specification information in the MCC and microinstruction shown in the figure, Figure 3 is a bit configuration diagram of the operation width specification field in the MCC, and Figure 4 is the MCC.
FIG. 5 is a bit configuration diagram of an operation width specification field in a microinstruction. 6 is a bit configuration diagram of an operation designation field in a microinstruction, FIG. 7 is a bit configuration diagram of an operation signal sent from the operation processing signal generation circuit of FIG. 1 to the operation circuit of FIG. 1,
8 is a characteristic diagram of the byte position identification signal sent from the arithmetic processing signal generation circuit of FIG. 1 to the arithmetic circuit of FIG. 1;
The figure is a characteristic diagram of the write instruction signal sent from the arithmetic processing signal generation circuit of Fig. 4 to the register of Fig. 1, and Fig. 1O is a characteristic diagram of the write instruction signal sent from the arithmetic processing signal generation circuit of Fig. 1 to the state signal selection circuit of Fig. 1. FIG. 3 is a characteristic diagram of a state signal selection signal sent to the. FIG. 11 is a diagram showing the difference in input and output signals of the arithmetic circuit according to the byte position identification signal, FIG. 12 is a block diagram of a conventional arithmetic processing device, and FIG. 13 is a detailed diagram of the arithmetic circuit of FIG. 12.
FIG. 14 is a detailed diagram of the control circuit shown in FIG. 13. FIG. 15 is an explanatory diagram of signals selected by the control circuit of FIG. 14. lO; read-only storage device (generation circuit). ll; Arithmetic processing signal creation circuit (switching circuit). 12, 13; Arithmetic circuit. 14.15. register. 18: Status signal selection circuit. 17; Status signal set circuit.

Claims (1)

[Claims] In a microprogram-controlled arithmetic processing device, a generation circuit (10) generates operation designation information consisting of the type of operation of the instruction and the data width of the operation according to the instruction code.
and an arithmetic processing signal generation circuit (11) that selects either the microinstruction or the generation circuit (10) according to the content of the microinstruction, and an arithmetic processing circuit (12, 13) that performs an arithmetic operation in accordance with the selected output. an arithmetic processing device, wherein either a microinstruction or an output of the generation circuit (10) is selected by the microinstruction itself, and an operation is specified to the arithmetic circuit (12, 13) based on the result. .