JPS61182251A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS61182251A JPS61182251A JP60022842A JP2284285A JPS61182251A JP S61182251 A JPS61182251 A JP S61182251A JP 60022842 A JP60022842 A JP 60022842A JP 2284285 A JP2284285 A JP 2284285A JP S61182251 A JPS61182251 A JP S61182251A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- layer
- contact
- width
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、特に牛擲体集積回路装置（以下ＩＣ）に形成
される抵抗体に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a resistor formed in an integrated circuit device (hereinafter referred to as IC).
従来、ＩＣ内に形成される抵抗は第５図および第６図に
示す構造が多く用いられている。第５図は平面図、第６
図は第５図のＸ軸に対する断面図であり、■および９は
抵抗体としてのＰ型不純物層であり、ｌを抵抗部、９を
コンタクト部とする。Conventionally, the structures shown in FIGS. 5 and 6 have often been used for resistors formed in ICs. Figure 5 is a plan view, Figure 6
The figure is a sectional view taken along the X-axis in FIG. 5, where 2 and 9 are P-type impurity layers serving as resistors, l is a resistance portion, and 9 is a contact portion.
４は素子分離用のｐｒｉｇ、ｓはＰ型基板、６はＮ型エ
ピタキシャル層、７は高濃度Ｎ型埋込層である。4 is a prig for element isolation, s is a P type substrate, 6 is an N type epitaxial layer, and 7 is a high concentration N type buried layer.
ここでコンタクト窓２を抵抗体１．９の内側にするのは
、ＩＣ製造工程におけるマスクの目合わせズレやエツチ
ングのバラツキ等により、コンタクト窓が抵抗体から外
れて、アルミニウム配？ｆ＃８が抵抗体の周囲のＮ型エ
ビタキンヤル層６と接触することを防ぐためである。−
力、抵抗体とアルミニウム配線８を接続する部分の抵抗
は、抵抗の設計上小さい刀が望筐しいため、コンタクト
窓２６あまり小さくすることができない。したがって。Here, the reason why the contact window 2 is placed inside the resistor 1.9 is because the contact window is separated from the resistor due to misalignment of the mask in the IC manufacturing process, variations in etching, etc., and the contact window 2 is placed inside the resistor 1.9. This is to prevent f#8 from coming into contact with the N-type epitaaxial layer 6 around the resistor. −
The contact window 26 cannot be made very small because the resistance of the portion connecting the resistor and the aluminum wiring 8 is desirably small due to the design of the resistor. therefore.
通常は、抵抗体としてのＰ型不純物の領域を抵抗部１よ
りも大きくしたコンタクト部９を作り、この部分にコン
タクト窓を設けている。Usually, a contact section 9 is formed in which the P-type impurity region serving as a resistor is larger than the resistor section 1, and a contact window is provided in this section.
ところが、従来の抵抗の構造では抵抗部ｌよシも幅の広
いコンタクト部９を設けなければならないため、抵抗体
の面積が大さくなるうえ、第７図ように複数の抵抗を並
べたときの抵抗間距離）１０けコンタクト部間の距離と
なるため、抵抗体の形成に必要な領域が大きくなｐ、こ
の結果、ＩＣのペレットサイズを大きくするという次点
を有していた。However, in the conventional resistor structure, it is necessary to provide a contact portion 9 which is wider than the resistor portion L, which increases the area of the resistor and also makes it difficult to arrange the resistor when multiple resistors are arranged as shown in Fig. 7. Since the distance between the contact parts is 10 times the distance between the resistors (distance between resistors), the area required for forming the resistor is large, and as a result, the pellet size of the IC is increased.
本発明による抵抗は、コンタクト窓の幅が抵抗体の幅以
上であることを特徴とし、これによって抵抗の占有面積
が小さくなる。The resistor according to the present invention is characterized in that the width of the contact window is greater than or equal to the width of the resistor, thereby reducing the area occupied by the resistor.
本発明を実施例により説明する。 The present invention will be explained by examples.
第１図は本発明の一実施例による抵抗体の平面図、第２
図は第１図のＸ軸に対する断面図であわ、第５図および
第６図との共通部分は同じ番号を使っている０第１図か
ら明らかなように、コンタクト窓２と抵抗部ｌの幅を同
じにしてお！０、Ｌ、たがって従来の抵抗体よりもコン
タクト部のぶんだけ小ざくできる０また、第４図のよう
に抵抗体を並べる場合も、抵抗間距離１０は抵抗部１の
距離で決まるため、抵抗を形成する領域も小さくてすむ
。FIG. 1 is a plan view of a resistor according to an embodiment of the present invention, and FIG.
The figure is a sectional view taken along the X-axis in Figure 1, and the same numbers are used for parts common to Figures 5 and 6.0 As is clear from Figure 1, the contact window 2 and the resistor l. Make sure the width is the same! 0, L, so it can be made smaller by the amount of the contact part than a conventional resistor.0Also, when resistors are arranged as shown in Figure 4, the distance between the resistors 10 is determined by the distance of the resistor part 1, so The area in which the resistor is formed can also be small.
ここで、マスクの目合わせズレ等によりコンタクト窓２
が抵抗部１からズして、アルミニウム配線８とＮ型エピ
タキシャル層６が接触することが考えられる。このとき
、層６の濃度は低いので、配線８と層６とはオーミック
コンタクトを形成せず、これらはショットキーバリア接
合を形成するＯ換言すれば、層６の濃度はショク）キー
接合を形成するように低くなっている。したがって、抵
抗部ｌとＮ型エピタキシャル層６０間に第３図で示すよ
うにショットキーバリアダイオード（以下８ＢＤ）１１
が形成されることになる。ショットキー接合を形成しか
つ他のデノくイスの電気的特性を劣化させないエピタキ
シャル層の濃度Ｖｉｉｘｔｏ１４乃至Ｉ Ｘ ｌ ０ｔ
ｙｃＩＩＬ−ｓが望ましいＯＮ型エピタキシャル層６は
ＩＣの最高電位、通常はＶ 電源端子に接続されている
０よって、８ＢＤ１１の耐圧以下の電源電圧で使用する
ＩＣであれば、何ら支障なく抵抗体は使用できる０通常
８ＢＤの耐圧は数十Ｖであり、また最近のＩＣは電池駆
動が主流となっており、はとんどのＩＣが十数Ｖ以下の
電源電圧となっているため、本発明による抵抗体は、は
とんどのＩＣに適用可能である。Here, due to misalignment of the mask, contact window 2
It is conceivable that the aluminum wiring 8 and the N-type epitaxial layer 6 come into contact with each other due to the deviation from the resistive portion 1 . At this time, since the concentration of layer 6 is low, the wiring 8 and layer 6 do not form an ohmic contact, and they form a Schottky barrier junction.In other words, the concentration of layer 6 is low, so they form a Schottky barrier junction. It's getting lower. Therefore, as shown in FIG.
will be formed. Epitaxial layer concentration that forms a Schottky junction and does not deteriorate the electrical characteristics of other devices
The ON type epitaxial layer 6, which is preferably ycIIL-s, is connected to the highest potential of the IC, usually V. Therefore, if the IC is used at a power supply voltage lower than the withstand voltage of 8BD11, the resistor can be used without any problem. The withstand voltage of usable 8BD is several tens of V, and recent ICs are mainly driven by batteries, and most ICs have a power supply voltage of less than a dozen V. Therefore, the present invention Resistors are applicable to most ICs.
上記内科は、コンタクト窓２の幅を抵抗部ｌの幅よりも
積極的に大きくした場合も同様である。The same applies to the case where the width of the contact window 2 is actively made larger than the width of the resistance part l.
また、層６がＰ型の場合は、ＳＢＤのアノード側がＩＣ
の最低電位にバイアスされることになるので、やはり使
用できる０
〔発明の効果〕
以上説明したように本発明によれば、抵抗体及び抵抗体
を形成するのに必賛な領域が縮小され、ＩＣのベレ、ト
面積を縮小する効果がある０上記実施例はバイポーラＩ
Ｃであるが、Ｍ０８ＩＣにも適用され得る０In addition, if layer 6 is P type, the anode side of the SBD is the IC
[Effects of the Invention] As explained above, according to the present invention, the resistor and the area necessary for forming the resistor are reduced, The above embodiment is a bipolar IC which has the effect of reducing the area of the IC.
C, but can also be applied to M08IC 0
第１図は本発明の一実施例による抵抗体の平面図、第２
図は第１図のＸ軸に対する断面図、第３図はコンタクト
窓がズした場合の等価回路図、第４図は複数の抵抗体を
並べた場合の平面図、第５図および嬉６図は夫々従来例
の平面図および断面図、第７図は複数抵抗体の平面図で
ある０１・・・・・・抵抗体ｃＰ型）、２・・・・コン
タクト窓。
３・・・絶縁１−１４・・・・・素子分離用Ｐ層、５・
・・・・Ｐ型基板、６・・・・・Ｎ型エビタキンヤル層
、７・・・・Ｎ型高濃度埋込層、８・・・・・・アルミ
ニウム配線％９・・・・・コンタクト部、１０・・・・
・抵抗間距離、１１・・・・・・寄生ショットキーバリ
アダイオード〇
６一FIG. 1 is a plan view of a resistor according to an embodiment of the present invention, and FIG.
The figure is a sectional view taken along the X-axis in Figure 1, Figure 3 is an equivalent circuit diagram when the contact window is misaligned, Figure 4 is a plan view when multiple resistors are lined up, Figures 5 and 6. 7 is a plan view and a cross-sectional view of a conventional example, respectively, and FIG. 7 is a plan view of a plurality of resistors. 01...resistor cP type), 2... contact window. 3... Insulation 1-14... P layer for element isolation, 5.
... P type substrate, 6 ... N type Evita layer, 7 ... N type high concentration buried layer, 8 ... Aluminum wiring %9 ... Contact part , 10...
・Distance between resistors, 11... Parasitic Schottky barrier diode 〇61
Claims (1)
前記抵抗体の幅以上であることを特徴とする半導体装置
。The width of the opening for connecting the resistor and conductive wiring is
A semiconductor device characterized in that the width is greater than or equal to the width of the resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60022842A JPS61182251A (en) | 1985-02-08 | 1985-02-08 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60022842A JPS61182251A (en) | 1985-02-08 | 1985-02-08 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61182251A true JPS61182251A (en) | 1986-08-14 |
Family
ID=12093960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60022842A Pending JPS61182251A (en) | 1985-02-08 | 1985-02-08 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61182251A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01167057U (en) * | 1988-05-13 | 1989-11-22 | ||
| JP2015130428A (en) * | 2014-01-08 | 2015-07-16 | 富士通セミコンダクター株式会社 | Semiconductor device and method of manufacturing the same |
-
1985
- 1985-02-08 JP JP60022842A patent/JPS61182251A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01167057U (en) * | 1988-05-13 | 1989-11-22 | ||
| JP2015130428A (en) * | 2014-01-08 | 2015-07-16 | 富士通セミコンダクター株式会社 | Semiconductor device and method of manufacturing the same |
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