JPS61187367A - Output circuit of charge coupled device - Google Patents

Output circuit of charge coupled device

Info

Publication number
JPS61187367A
JPS61187367A JP60026359A JP2635985A JPS61187367A JP S61187367 A JPS61187367 A JP S61187367A JP 60026359 A JP60026359 A JP 60026359A JP 2635985 A JP2635985 A JP 2635985A JP S61187367 A JPS61187367 A JP S61187367A
Authority
JP
Japan
Prior art keywords
output
circuit
voltage
channel
coupled device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60026359A
Other languages
Japanese (ja)
Inventor
Masayuki Matsunaga
誠之 松長
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60026359A priority Critical patent/JPS61187367A/en
Publication of JPS61187367A publication Critical patent/JPS61187367A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00Charge transfer devices
    • H10D44/40Charge-coupled devices [CCD]
    • H10D44/45Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H10D44/454Output structures

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To obtain an output circuit in which electric current flowing in a follower circuit is small and the zero level period of the output voltage and signal period are long, by a method wherein a source follower circuit using P channel MOSFET is connected to an output circuit of a charge coupled device which is an N-type transmitting channel. CONSTITUTION:A floating connecting type detecting circuit is made by providing a source follower circuit 107 using a P channel MOSFET in the output circuit of the charge coupled device which is the N-type transmitting channel. Drain voltage VD is applied through the intermediary of a load resistor 110 to a drain 108 of this P channel MOSFET, and a source 109 is grounded, and an output terminal 111 is taken out from between the resistor 110 and the drain 108. A signal load under the last stage transmitting electrode 101, is transmitted in a floating diffusion area 103 through an output gate 102 when applying voltage VP3 becomes large, and increased load at this rate is accumulated. Accordingly, electric potential of the area 103 is determined by the electric static capacity C, signal load volume Q, and reset level VR, and the relation of Vd= VR-Q/C is established.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、電荷結合素子の出力回路に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to an output circuit for a charge coupled device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

電荷結合素子の信号である電荷を電圧に変換し検出する
出力回路の一つとしてフローティング接合形検出回路が
知られている。これは、信号電荷(Q)がpn接合の空
乏層容量及びMOSFETのゲート容量などの容量(C
)に蓄積されQ/Cの電位変化を鐸起し、更にこの電位
変化をソースホロア回路の出力電圧として得るものであ
る。
A floating junction detection circuit is known as one of the output circuits that converts charge, which is a signal from a charge-coupled device, into voltage and detects it. This is because the signal charge (Q) is the depletion layer capacitance of the pn junction and the capacitance (C
), which causes a potential change in Q/C, and further obtains this potential change as the output voltage of the source follower circuit.

第5図は従来の一例である70−ティング接合形検出回
路の構成図である。転送チャネルがn形である電荷転送
素子の最終段転送電極(501)の隣に出力電圧(vO
)を印加する出力ゲート電極(502)を設け、更にそ
の隣にnチャネルMO8FETを設ける。とのれチャネ
ルMO8FETにおいてソース領域に相当するフローテ
ィング拡散領域(503)はノースホロア回路(507
)のnチャネルMO8FETのゲー) (504)と接
続され、ドレイン(506)にはリセットドレイン電圧
(vBD)が、ゲート(505)にはパルス波形である
リセット電圧(VB2 ’)が印加される。
FIG. 5 is a block diagram of a conventional 70-Ting junction type detection circuit. An output voltage (vO
) is provided, and an n-channel MO8FET is provided next to it. In the channel MO8FET, the floating diffusion region (503) corresponding to the source region is connected to the north follower circuit (507).
) of the n-channel MO8FET (504), a reset drain voltage (vBD) is applied to the drain (506), and a reset voltage (VB2') having a pulse waveform is applied to the gate (505).

ソースホロア回路(507)ではnチャネルMO8FI
3Tのドレイン(508)にドレイン電圧(VD)を印
加しソース(509)は負荷抵抗(510)を介して接
地するっ出力端子(511)はソース(509)と負荷
抵抗(510)の間から取る。転送される信号電荷量に
より変化するフローティング拡散領域(503)の電位
をnチャンネルMO8FETを用いたソースホロア回路
(507)により出力電圧に変換する出力回路である。
In the source follower circuit (507), an n-channel MO8FI
The drain voltage (VD) is applied to the drain (508) of the 3T, and the source (509) is grounded via the load resistor (510).The output terminal (511) is connected between the source (509) and the load resistor (510). take. This is an output circuit that converts the potential of the floating diffusion region (503), which changes depending on the amount of signal charge transferred, into an output voltage by a source follower circuit (507) using an n-channel MO8FET.

しかし゛、このような従来の出力回路において、消費電
力を少なくするためにソースホロア回路(507)の負
荷抵抗(510)を大きくすると以下のような問題点が
生じる。
However, in such a conventional output circuit, when the load resistance (510) of the source follower circuit (507) is increased in order to reduce power consumption, the following problems occur.

第6図に、最終段転送電極の印加電圧(Vp3)とリセ
ットゲートの印加電圧(VB2 )とソースホロア回路
の負荷抵抗が小さい場合の出力電圧(Vou を人)と
大きい場合の出力電圧(vout B )の電圧波形の
関係を示す。
Figure 6 shows the voltage applied to the final stage transfer electrode (Vp3), the voltage applied to the reset gate (VB2), the output voltage when the load resistance of the source follower circuit is small (Vou is human), and the output voltage when it is large (vout B). ) shows the relationship between voltage waveforms.

フローティング拡散領域(503)とリセット電圧) 
(505)は容量結合しておシ、リセットゲート(50
5’)にリセット電圧(va s )が印加されると7
0−ティング拡散領域(503)にも電圧が印加され出
力電圧にリセットノイズ(61’)が生じる。リセット
ノイズ(61)ノ立ち上り(At 、A2 、As )
 において、nチャネルMO8ITはON状態となりド
レイン電圧(VD)が出力端子(511)より出力され
る。リセットノイズ(61)の立ち下り(Bl、B2.
B3.B4,85)におI/にテ、nチャネルMO8F
ETはOFF状態となり、ソース(509)及び出力端
子(511)の浮遊容量に蓄積された電荷が負荷抵抗(
510)を介して接地電位に移動するので負荷抵抗(5
10)によりリセットレベルに下がるまでの時間を用す
るため出力電圧の立ち下りが緩やかKなる。従って、第
6図からもわかるようにソースホロア回路(507)の
負荷抵抗(510)が大きい場合の出力電圧(Vout
 B) Kおける零レベル期間(TzatB、Tzsz
B)と信号期間(T561B、T862B)は負荷抵抗
(510)が小さい場合の出力電圧(Vout人)にお
ける零レベル期間(T26□人、Tz62人)と信号期
間(Tss1人、Ts s 2A)と比較すると短かく
なる。
floating diffusion region (503) and reset voltage)
(505) is capacitively coupled and reset gate (50
7 when the reset voltage (va s ) is applied to
A voltage is also applied to the 0-ting diffusion region (503) and reset noise (61') is generated in the output voltage. Rise of reset noise (61) (At, A2, As)
At this time, the n-channel MO8IT is turned on and the drain voltage (VD) is output from the output terminal (511). Falling edge of reset noise (61) (Bl, B2.
B3. B4, 85) to I/Ni Te, n channel MO8F
ET is in the OFF state, and the charges accumulated in the stray capacitance of the source (509) and output terminal (511) are transferred to the load resistance (
510) to the ground potential, the load resistance (5
10), the fall of the output voltage becomes gradual because the time required for the voltage to drop to the reset level is used. Therefore, as can be seen from FIG. 6, when the load resistance (510) of the source follower circuit (507) is large, the output voltage (Vout
B) Zero level period at K (TzatB, Tzsz
B) and the signal period (T561B, T862B) are the zero level period (T26□ person, Tz62 person) and the signal period (Tss 1 person, Ts s 2A) at the output voltage (Vout person) when the load resistance (510) is small. It is shorter in comparison.

出力電圧(VoutB)において零レベル期間(Tzs
xB。
The output voltage (VoutB) has a zero level period (Tzs
xB.

TzszB)と信号期間(T$61B、T862B)が
短かいと後段の信号処理が困難となり、又信号の電力も
低下してしまう。このため、電荷結合素子の出力回路の
特性が低下してしまう。
If the signal period (TzszB) and signal period (T$61B, T862B) are short, signal processing in the subsequent stage becomes difficult and the signal power also decreases. Therefore, the characteristics of the output circuit of the charge-coupled device deteriorate.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ソースホロア回路に流れる電流が小さ
く出力電圧の零レベル期間及び信号期間が長い電荷結合
素子のフローティング接合形検出回路を提供することに
あろう 〔発明の概要〕 本発明は、電荷結合素子の最終段転送電極の隣シに設け
られた出力ゲートと、最終段転送電極下に存在する信号
電荷を出力ゲート下の障壁を介して転送し蓄積するフロ
ーティング拡散領域と、この領域と電圧を印加したリセ
ットゲート下のチャネルを介して導通状態となるドレイ
ン領域と、ゲートがフローティング拡散領域に接続され
ているMOSFETを用いたソースホロア回路とから成
る電荷転送素子の出力回路において、電荷結合素子のチ
ャネルと反対導電形チャネルのMOSFETを用いたソ
ースホロア回路を有することを特徴とする電荷結合素子
の出力回路を提供すS。
An object of the present invention is to provide a floating junction detection circuit for a charge coupled device in which the current flowing through the source follower circuit is small and the zero level period and signal period of the output voltage are long. An output gate provided next to the final stage transfer electrode of the coupling element, a floating diffusion region that transfers and accumulates signal charges existing under the final stage transfer electrode via a barrier under the output gate, and a voltage In the output circuit of a charge transfer device, which consists of a drain region that becomes conductive through a channel under a reset gate to which a voltage is applied, and a source follower circuit using a MOSFET whose gate is connected to a floating diffusion region, Provided is an output circuit for a charge-coupled device characterized by having a source follower circuit using a MOSFET having a conductivity type opposite to that of the channel.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の一実施例を図面によって説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の実施例であるフローティング接合形検
出回路の構成図である。像形転送チャネルである電荷結
合素子の出力回路にpチャネルMO8FETを用いたソ
ースホロア回路(107)を設けたことを特徴とするも
のであるopチャネルMO8FFfTのドレイン(10
8)には負荷抵抗(110)を介してドレイン電圧(V
D)を印加する0ソ=ス(109)は接地する。出力端
子(111)は負荷抵抗(110)とドレイン(108
)の間から取る。
FIG. 1 is a block diagram of a floating junction type detection circuit according to an embodiment of the present invention. The drain (107) of an op-channel MO8FFfT is characterized in that a source follower circuit (107) using a p-channel MO8FET is provided in the output circuit of a charge-coupled device that is an image transfer channel.
8) is connected to the drain voltage (V
The 0 source (109) that applies D) is grounded. The output terminal (111) is connected to the load resistor (110) and the drain (108).
).

順次転送され最終段転送電極(101)下に存在する信
号電荷は、印加電圧(Vp3)がLになると出力ゲート
(102)を経てフローティング拡散領域(103)内
に転送される。フローティング拡散領域(103)とこ
の下の半導体におけるpn接合の空乏層容量とMOSF
ETのゲー) (104)の容量と70−テイング拡敵
領域(103)と出力ゲート(102)及びリセットゲ
ート(105)間の容量から成る全容量にこの転送され
た信号電荷量だけ増加した電荷が蓄積される。
The signal charges that are sequentially transferred and exist under the final stage transfer electrode (101) are transferred into the floating diffusion region (103) via the output gate (102) when the applied voltage (Vp3) becomes L. Floating diffusion region (103) and pn junction depletion layer capacitance in the semiconductor below and MOSF
The total capacitance consisting of the capacitance of (104) and the capacitance between the output gate (102) and reset gate (105) is increased by the amount of signal charge transferred. is accumulated.

従って、フローティング拡散領域(103)の電位(V
d)は、この領域における静電容量(C)と、この領域
に流入する信号電荷量(Q)と、この領域におけるリセ
ットレベル(VB)とで定まシ1、Vd= VR−Q/
C なる関係が成立する。なお、リセットゲート(105)
の印加電圧(VR8)がHになると、ブローティング領
域(103)内に転送された信号電荷はドレイン領域(
106)へ排出される。転送される信号電荷量により変
化する70−テイング拡教領域(103)の電位CVd
) ’r: pチャネルMO8FETを用いたソースホ
ロア回路(107)によシ出力電圧(vout) K変
換する。
Therefore, the potential (V
d) is determined by the capacitance (C) in this region, the amount of signal charge (Q) flowing into this region, and the reset level (VB) in this region1, Vd = VR-Q/
The relationship C holds true. In addition, the reset gate (105)
When the applied voltage (VR8) becomes H, the signal charges transferred into the bloating region (103) are transferred to the drain region (103).
106). Potential CVd of the 70-ting expansion region (103) that changes depending on the amount of signal charge transferred
) 'r: The output voltage (vout) is converted to K by a source follower circuit (107) using a p-channel MO8FET.

第2図及び第3図に、ソースホロア回路のpチャネルM
O8FETを含む電荷転送素子の出力回路装置の断面図
を示す。実際の素子としては第2図に示すような、n形
半導体基板中にp形つェルを形成し、この領域内に電荷
転送素子を形成する素子麦、又第3図に示すようなp形
半導体基板中にn形つェルを形成し、この領域内にソー
スホロア回路のpチャネルMO8FETを形成する素子
がある0第4図に、第1図に示した出力回路において、
最終段転送電極(101)の印加電圧(Vp3)とリセ
ットゲート(105)の印加電圧(V、、)と出力電圧
(vout)の電圧波形の関係を示す。70−テイング
拡敵領域(103)とリセットゲート(105)は容量
結合しておりリセットゲート(105)にリセット電圧
(V、、 )が印加されるとフローティング拡散領域(
103)にも電圧が印加され出力電圧にリセットノイズ
αDが生じる。リセットノイズ(財)の立ち上り(Cx
 、C2,C3)において電荷結合素子の転送チャネル
と反対導電形であるpチャネルMO8FETはOFF状
態となシトレイン電圧(vD)が負荷抵抗(110)を
介して出力端子(111)より出力されるつりセットノ
イズIの立と下がり(DI 、D2 、D3 、D4 
、D5 )において電荷結合素子の転送チャネルと反対
導電形であるpチャネルMo5i’g’rはON状態と
な′シリセットレベルに急激に下がる。
2 and 3 show the p-channel M of the source follower circuit.
A cross-sectional view of an output circuit device of a charge transfer element including an O8FET is shown. Actual devices include the device shown in Figure 2, in which a p-type well is formed in an n-type semiconductor substrate, and a charge transfer element is formed within this region, and the device shown in In the output circuit shown in FIG. 1, an n-type well is formed in a type semiconductor substrate, and an element forming a p-channel MO8FET of a source follower circuit is located in this region.
The relationship between the applied voltage (Vp3) of the final stage transfer electrode (101), the applied voltage (V, , ) of the reset gate (105), and the voltage waveform of the output voltage (vout) is shown. The 70-ting enemy expansion region (103) and the reset gate (105) are capacitively coupled, and when a reset voltage (V, ) is applied to the reset gate (105), the floating diffusion region (
103) is also applied, and reset noise αD is generated in the output voltage. Rise of reset noise (goods) (Cx
, C2, C3), the p-channel MO8FET, which is of the opposite conductivity type to the transfer channel of the charge-coupled device, is in the OFF state. The rise and fall of set noise I (DI, D2, D3, D4
, D5), the p-channel Mo5i'g'r, which is of the conductivity type opposite to the transfer channel of the charge-coupled device, is turned on and rapidly drops to the reset level.

従って、消費電力を少なくするため負荷抵抗(110)
を大きくしても出力電圧における零レベル期間(Tz4
1.Tz42)及び信号期間(Ts4t #TS42)
は短かくならず、後段の信号処理が行ないやすく、又信
号の電力も大きくなる。
Therefore, in order to reduce power consumption, the load resistance (110)
Even if the output voltage is increased, the zero level period (Tz4
1. Tz42) and signal period (Ts4t #TS42)
does not become shorter, signal processing at the subsequent stage is easier to perform, and the power of the signal becomes larger.

なお1本発明は上述した実施例に限定されるものでなく
、その要旨を脱しない範囲で変更してもよい。例えば半
導体基板の導電形を反対にしてもよい0又、ソースホロ
ア回路は最も基本的な回路であるため電荷転送チャネル
と反対導電形チャネルのMOSFETを用いて他の回路
設計も可能であるO 〔発明の効果〕 本発明によれば電荷結合素子のチャネルと反対導電形チ
ャネルのMO81Tt−用いたソースホロア回路を用い
たことにより、低消費電力で出力電圧の零レベル期間及
び信号期間が長い電荷結合素子のフローティング接合形
検出回路を得ることができる0
Note that the present invention is not limited to the embodiments described above, and may be modified without departing from the spirit thereof. For example, the conductivity type of the semiconductor substrate may be reversed.Also, since the source follower circuit is the most basic circuit, other circuit designs are possible using MOSFETs with channels of conductivity type opposite to the charge transfer channel. According to the present invention, by using a source follower circuit using an MO81Tt channel having a conductivity type opposite to that of a charge-coupled device channel, a charge-coupled device with low power consumption and a long output voltage zero level period and long signal period can be realized. A floating junction type detection circuit can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す電荷結合素子の出力回
路の構成図、第2図及び第3図は本発明の一実施例を示
すソースホロワ回路のMOSFETを含む電荷結合素子
の出力回路の断面図、第4図は本発明の一実施例におけ
る最終段転送電極に印加する電圧(Vp3) s  リ
セット電圧(vRs)及び出力電圧(vOLlt)との
関係を示す電圧波形図、第5図は従来の一例を示す電荷
結合素子の出力回路構成図、第6図は従来の一例におけ
る最終段転送電極に印加する電圧(vp3) h リセ
ット電圧(V、、)及び出力電圧(vOLltlp v
out2 )との関係を示す電圧波形である。 101.501・・・最終段転送電極、102、502
・・・出力ゲート、 103.503・・・、・・フローティング拡散領域、
104.504・・・ソースホロア回路のMOSFET
のゲート、105.505・・・リセットゲート、10
6.506・・・ドレイン、 107.507・・・ソースホロア回路、108.50
8・・・ソースホロア回路のMOSFETのドレイン、
109.509・・・ソースホロア回路のMOSFET
のソース、110.510・・・負荷抵抗、 111.511・・・出“力、端子。 第1図 第2図 第3図 ■ s4図 第5図 第6図
FIG. 1 is a configuration diagram of an output circuit of a charge coupled device showing an embodiment of the present invention, and FIGS. 2 and 3 are output circuits of a charge coupled device including a MOSFET of a source follower circuit showing an embodiment of the present invention. 4 is a voltage waveform diagram showing the relationship between the voltage (Vp3) s reset voltage (vRs) and the output voltage (vOLlt) applied to the final stage transfer electrode in one embodiment of the present invention, and FIG. 5 6 is a configuration diagram of an output circuit of a charge-coupled device showing a conventional example, and FIG. 6 shows a voltage (vp3) applied to the final stage transfer electrode in a conventional example.
It is a voltage waveform showing the relationship with out2). 101.501...Final stage transfer electrode, 102, 502
...output gate, 103.503..., floating diffusion region,
104.504... Source follower circuit MOSFET
gate, 105.505...reset gate, 10
6.506...Drain, 107.507...Source follower circuit, 108.50
8... Drain of MOSFET of source follower circuit,
109.509... Source follower circuit MOSFET
Source, 110.510...Load resistance, 111.511...Output, terminal. Figure 1 Figure 2 Figure 3■ s4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims]  電荷結合素子の最終段転送電極に隣接して設けられた
出力ゲートと、この出力ゲート下の障壁を介して転送さ
れた前記最終段転送電極下に存在する信号電荷が蓄積さ
れるフローティング拡散領域と、電圧を印加したリセッ
トゲート下のチャネルを介して前記フローティング拡散
領域と導通状態となるドレイン領域と、前記フローティ
ング拡散領域に接続されているゲートを有するMOSF
ETを用いたソースホロア回路とから成る電荷転送素子
の出力回路において、前記ソースホロア回路に用いられ
るMOSFETのチャネルが前記電荷結合素子の転送チ
ャネルと反対導電形であることを特徴とする電荷結合素
子の出力回路。
an output gate provided adjacent to a final-stage transfer electrode of a charge-coupled device; and a floating diffusion region in which signal charges existing under the final-stage transfer electrode transferred via a barrier under the output gate are accumulated. , a MOSF including a drain region that is electrically connected to the floating diffusion region through a channel under a reset gate to which a voltage is applied, and a gate that is connected to the floating diffusion region.
An output circuit of a charge transfer device comprising a source follower circuit using an ET, wherein a channel of a MOSFET used in the source follower circuit is of an opposite conductivity type to a transfer channel of the charge coupled device. circuit.
JP60026359A 1985-02-15 1985-02-15 Output circuit of charge coupled device Pending JPS61187367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60026359A JPS61187367A (en) 1985-02-15 1985-02-15 Output circuit of charge coupled device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60026359A JPS61187367A (en) 1985-02-15 1985-02-15 Output circuit of charge coupled device

Publications (1)

Publication Number Publication Date
JPS61187367A true JPS61187367A (en) 1986-08-21

Family

ID=12191287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60026359A Pending JPS61187367A (en) 1985-02-15 1985-02-15 Output circuit of charge coupled device

Country Status (1)

Country Link
JP (1) JPS61187367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179276A (en) * 1989-12-06 1991-08-05 Mitsubishi Electric Corp Charge detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179276A (en) * 1989-12-06 1991-08-05 Mitsubishi Electric Corp Charge detection circuit

Similar Documents

Publication Publication Date Title
JPH084136B2 (en) Charge transfer device
JPH0159772B2 (en)
US4998265A (en) Method of driving a charge detection circuit
JPS58104527A (en) Flashing analog-to-digital converter
EP0280097B1 (en) Charge transfer device with booster circuit
JPH033391B2 (en)
JPS61187367A (en) Output circuit of charge coupled device
JPH04373136A (en) Charge coupled device
US4350902A (en) Input stage for a monolithically integrated charge transfer device which generates two complementary charge packets
JPS6276813A (en) Insulation gate schmitt circuit
JPH04326849A (en) Image sensor
JP2669009B2 (en) Voltage comparison circuit
JPS61193484A (en) Semiconductor device
JPS5821360B2 (en) Denkatensou Sochi
JP2965568B2 (en) Charge detection device
JPS61268053A (en) Booster circuit
JPH03179276A (en) Charge detection circuit
JPS61184979A (en) Output circuit of charge transfer device
JPS60165760A (en) Charge transfer device
JPS6213827B2 (en)
JP3024276B2 (en) Charge transfer element
JPS5856465A (en) charge transfer device
JPH0427697B2 (en)
JPH0439804B2 (en)
JPH03101364A (en) Photoelectric converter