JPS61192U - Dynamic. drive display circuit - Google Patents
Dynamic. drive display circuitInfo
- Publication number
- JPS61192U JPS61192U JP1984083841U JP8384184U JPS61192U JP S61192 U JPS61192 U JP S61192U JP 1984083841 U JP1984083841 U JP 1984083841U JP 8384184 U JP8384184 U JP 8384184U JP S61192 U JPS61192 U JP S61192U
- Authority
- JP
- Japan
- Prior art keywords
- display
- dynamic
- display circuit
- ram
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図はこの考案の一実施例によるダイナミック・ドライブ
表示回路のブロック図である。
10・・・・・・CPU, 1 2・・・・・・RA
M,l 4・・・・・・アドレスカウンタ、16・・・
・・・表示器、18・・・・・・発振器、20・・・・
・・ゲート、22・・・・・・ゲート、24・・・・・
・表示制御用デコーダ。The figure is a block diagram of a dynamic drive display circuit according to an embodiment of the invention. 10...CPU, 1 2...RA
M, l 4...Address counter, 16...
...Indicator, 18...Oscillator, 20...
...Gate, 22...Gate, 24...
・Decoder for display control.
Claims (1)
素子にダイナミック●ドライブによって表示する表示回
路であって、表示データを記憶するためのRAMと、こ
のRAMに記憶された表示データを1ワードづつ順次読
み出して上記表示器にダイナミックかつサイクリックに
表示させるためのアドレスカウンタと、このアドレスカ
ウンタの歩進信号を与える発振器と、上記アドレスカウ
ンタによる上言び臥Mのアドレツシングを禁止すると同
時に、上記CPUにより上記RAMに表示データを書き
込むのを許容するゲート回路とを備えてなるダイナミッ
クφドライブ表示回路。This is a display circuit that displays display data given from a CPU on a large number of display elements of a display device using a dynamic drive, and includes a RAM for storing display data, and a display circuit that sequentially stores the display data stored in this RAM one word at a time. an address counter for dynamically and cyclically displaying the data on the display; an oscillator for providing an increment signal for the address counter; A dynamic φ drive display circuit comprising a gate circuit that allows display data to be written into the RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984083841U JPS61192U (en) | 1984-06-06 | 1984-06-06 | Dynamic. drive display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984083841U JPS61192U (en) | 1984-06-06 | 1984-06-06 | Dynamic. drive display circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192U true JPS61192U (en) | 1986-01-06 |
Family
ID=30632828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984083841U Pending JPS61192U (en) | 1984-06-06 | 1984-06-06 | Dynamic. drive display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04112224A (en) * | 1990-08-31 | 1992-04-14 | Sharp Corp | Controller for display device |
-
1984
- 1984-06-06 JP JP1984083841U patent/JPS61192U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04112224A (en) * | 1990-08-31 | 1992-04-14 | Sharp Corp | Controller for display device |
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