JPS61193190A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control device, and more particularly to a circuit for writing video data into a storage unit.

2. Description of the Related Art Conventionally, as shown in FIG. 4, this type of display control device has a central processing unit (CPU), a data register 3 connected to each IK, an address register 5, and a video data storage section connected to both. 6, when writing to the video data storage unit 6, the CPU 1 sends the address and data to the address register 5 and data register 3 every time for each writing unit of video data, and writes data to the video data storage unit 6 for all parts that require screen rewriting. CPU l access was required. In other words, access intervention by the CPU 1 is required as many times as the amount of data required for image rewriting divided by the amount of data per unit of rewriting, regardless of the content of the data.

For this reason, crux has the disadvantage that the time is spent on transferring video data, and during this time the execution of other programs is interrupted.

Problems to be Solved by the Invention An object of the present invention is to provide a display control device that solves the above-mentioned drawback, that is, the amount of time the CPU spends on transferring video data.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a data register for holding data sent from the CPU, and video data to be displayed on a display device using the contents of this data register as input. an address register that holds an address for writing the contents of the data register into the video data storage section; and an end address register that holds the last address for sequentially writing the contents of the data register; A comparison circuit that detects a match between the contents of the end address register and the address register, a flip 7C1y that is reset by the result of the comparison circuit, an address space register that holds a value to be added to the address register, and an address register and an address space register. An adder circuit that adds the contents of , and the output result of the adder circuit and the CPU
A configuration is adopted in which the input is the address of the video data storage section sent from the flop, and the contents of the Aritz flop (and a selection circuit that selects one of these two inputs and sends it to the input of the address register).

Operation The present invention has a Kll construction as described above, so if there is a continuous pattern in the image data information, this final address value is set in the end address register, 1 is set in the address space register, and the address is added by the sequential addition circuit. Processing is performed within the control device until the value of the address register matches the final address, and the data is written to the video data storage section.In the case of an alternating pattern, the final address is similarly set in the end address register, and the address In order to set 2t- in the space register, perform addition in the same way, perform processing within the control device, and write to the video data storage unit.
During this time, no load is placed on the CPU.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of an embodiment of the present invention, the display device of the present invention includes a data register 3 connected to a CPUI, an end address register 7, an address space register 10, and a selection circuit 13. and an address comparison circuit 8 that compares the outputs of the address register 5 and the end address register 7.
When the comparison result of the comparator circuit 8 matches, the flip 70 knob 9, the address register 5, and the address space register 10 are set by the signal 16 from the CPUI.
an adder circuit 11 that adds the outputs of the adder circuit 11 and a selector circuit 13 that selects the output 17 of the adder circuit 11 and the address bus 4 using the output of the 7-lip flop 9 and inputs the selected data to the address register 5.
, a selection circuit 19 that selects the output of the address register 5 and the output of the video data read address generation circuit 12, and a video data storage section 6 that receives the output of the data register 3 and the output of the selection circuit 19. There/Next, C
Referring to FIG. 2 as an example of the information desired to be displayed on the B and T screens, in this case, conventionally each

An access from the CPU is required for each piece of data, and in the case of this figure, 35 accesses from the CPU are required.

In this figure, data 5 and 8 are used to display the same value continuously. According to the invention, data 1-4.6,7
, 9, and 10 conventionally require access from the CPU, but since data 5°8 is continuous, the data that conventionally required access from the CPU 13.14 times each , you only need to access each one once! The video data is stored in the video data storage unit at high speed without imposing a burden on the CPUK.

Next, referring to Figure 3, it is not a series of the same data,
This is an alternating pattern of data 5 and 6 and data 8 and 9. In such a case, set the pattern of data 5 to 2 in the address space register 1G, write every other data 5 to the video data storage unit 6, then reset the address and write data 6 in the same way. By writing every other data to the video data storage section, the number of accesses from the CPU can be reduced. A similar writing method is applied to the alternating pattern of data 8°9 in the case of FIG.

Therefore, the CPU can perform processes other than writing Eirin data during this time, increasing overall processing efficiency, especially when writing Eirin data with regularity as shown in Figures 2 and 3. Great effects can be expected.

Next, explanation will be given with reference to specific hardware shown in FIG. In the conventional operation, video data is sent from the CPU via the data bus 2 and stored in the data register 3. Further, the address of the video data is set in the address register 5 via the address bus 4. After that, the video data storage unit 6
to complete the write operation. According to this conventional method, the number of CPU accesses shown in FIG. 2 is 35. Second
When storing the video data shown in the figure in the video data storage unit 6,
In the present invention, data 1 to 4, 6, 7°9.10 are the same as the conventional data, but in the case of data 5, the value of data 5 is set in the data register 3, and the address value of data 5 is set. The fifth value of 5 is set in address register 5. Further, since data continuation 5 is consecutively imaged from the 5th to the 177th, its final address value 17 is set to the end address register 7 by the set signal 14. Additionally, a value of 1 is set as the address interval by the CPU to the address space register 10 through signal 15. In this state, data is written into the video data storage section 6 by the data register 3 and address register 5, and at the same time, a comparison circuit 8 detects a match between the contents of the address register 5 and the end address register 7, and a match is detected. case 7 lipflop 9
is reset. If they do not match, flip-flop 9 will not be reset. When the flip 70 knob 9 is reset, the continuous pattern writing is deemed to have ended, and the CPU is notified through the signal 15, and the address selection circuit 13 is also driven to select the address bus 4.

The continuous mode is started by setting the flip-flop 9 through the signal 16 from the CPU. That is, when normal CPU access is required, the 7-lip flop 9 is reset, and the 7-lip flop 9 is set by the set signal 16 in the continuous access mode.

Furthermore, in the continuous access mode, the contents of the address register 5 and the contents of the address space register 10, which is set to a value of 1 as the address interval, are added in an adder 11, and the result 17 is sent to the selection circuit 13. Since we are currently in the continuous access mode, the selection circuit 13 selects the addition result signal 17 using the signal 15 and sends it to the address register 5, and the address is updated every time the video data 3 is written to the video data storage section 6. . By performing address updating and end detection on the video data writing side in this way, the load on the CPU can be eliminated and high-speed writing can be realized.

. The above description has been made with reference to the case of FIG. 2, but in the case of the alternating pattern in FIG. Further, the video data read address generation circuit 12 is connected to the CR, T monitor 1
When displaying to 8, send the read address and selector 1
9 to send the contents of the video data storage section 6 to the CRT 18.

As described in detail, according to the present invention, by setting the continuous pattern range and address interval, regular continuous patterns can be written to the video data storage unit at high speed and without the intervention of the CPU. This has the effect of improving the processing efficiency of the system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of specific hardware showing an embodiment of the present invention, Figs. 2 and 3 are diagrams of a CRT screen showing the arrangement of video data, and Fig. 4 is a conventional example of hardware. FIG.

Claims (1)

[Claims] A data register connected between a central processing unit (hereinafter referred to as CPU) and a CRT display device and holding data sent out from the CPU, and video data to be displayed on the display device using the contents of this data register as input. and an address register that is connected to the CPU and holds an address for writing the contents of the data register to the video data storage section, an end address register that holds the last address whose contents are to be written continuously; a comparison circuit that detects a match between the contents of this end address register and the contents of the address register; a flip-flop that is set at the same time and reset by the comparison result of the comparison circuit; an address space register that is connected to the CPU and holds a value to be added to the address register; and the contents of the address register and the address space register are added. a selection circuit which receives the addition result of the addition circuit and the address of the video data storage unit sent from the CPU as input, selects one of the inputs according to the contents of the flip-flop, and sends it to the input of the address register; A display control device comprising: