JPS61196621A - Digital-analog converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital-to-analog converter that is used in an output circuit of a servo device or the like and requires linearity near the center.

(Prior technology) In recent years, digital systems have become mainstream in place of analog systems in the field of control, but the output to the drive unit is often output as analog signals, and in the case of digital systems, control signals are It converts digital to analog and outputs it to the drive unit.

Linearity is important as an input/output characteristic of a digital-to-analog converter (hereinafter referred to as a D/A converter), and it is a major problem to easily obtain linearity.

An example of the conventional D/A converter mentioned above will be described below with reference to the drawings.

FIG. 4 shows a conventional D/A converter, and here an 8-bit ladder resistance network type D/A converter will be explained. In the figure, 1 is a reference voltage source, 100
is a ladder resistance network consisting of resistors 101 to 10 with the same resistance value 2R and resistors 111 to 117 with the same resistance value R, and 200 is one end of each weighted resistor 101 to 108 of the ladder resistance network. A switch circuit group consisting of switches 201 to 208 connected to , 2 to 9 are digital signal input terminals, 2 being the lowest -E side and 9 being the lowest side. 10 is an operational amplifier that amplifies the D/A conversion output, 11 is a feedback resistor of the operational amplifier, 12 is a resistor for offset compensation of the operational amplifier, 13
and a D/A conversion output terminal. Switch 201 or 2
08 connects one end of each weighted resistor of the ladder resistance network to the reference voltage source 1 or the ground side depending on the level of the digital signal input to the input terminals 2 to 9. The resistance value of the feedback resistor 11 of the operational amplifier 10 is assumed to be 3R, which is three times the resistance value of the resistor ladder network 100 from 111 to 117.

The operation of the D/A converter configured as described above will be explained below.

First, it is assumed that [1,0000000] digital signals are input to the digital signal input terminals 2 to 9 from the uppermost side to the lowermost side. Here, the low level of the signal is set to "O", and the high level of the signal is set to "1". The switches 201 to 208 connect the resistors 201 to 208, which are weighted according to the pin 1, to the digital input signal.
1”, the digital input signal is output to the reference voltage source 1 side.
When ゛, connect to the ground side. Thus, the digital input signal connects switch 201 towards reference voltage source 1 and switches 202 to 208 to ground. The resistance value of resistors 101 to 110 is 2R, and the resistance value of resistor 1
Since the resistance value of 11 to 117 is R, the combined impedance at point A is R. If the voltage of the reference voltage source 1 is E, the voltage at point A is 173, and the voltage output to the D/A conversion output terminal 13 is the voltage of the input resistor 11 of the operational amplifier.
Since the resistance value of 0 is 2R1 and the resistance value of feedback resistor 11 is 3R, 1. /2*E, and an output corresponding to the most significant bit is obtained. The same thing can be said about the other signal input terminals 3 to 9, from signal input terminal 3 to signal input terminal 9.
The weight of the bit decreases towards .

When a digital signal of [00000001] is input to the digital signal input terminals 2 to 9 from the lowest to the lowest side, only the switch 208 is connected to the reference voltage source 1 side, and the other switches 201 to 9 are connected to the reference voltage source 1 side. 207 is grounded. Therefore, the voltage output to the D/A conversion output terminal 13 is 1/128*E, and an output corresponding to the least significant bit, that is, the first to eighth bits is obtained.

(Problems to be Solved by the Invention) In the above configuration, in order to obtain linearity in the output characteristics of the D/A converter, it is necessary to ensure the relative accuracy of the resistance that weights each bit. is important. However, it becomes difficult to ensure the relative accuracy of the resistor corresponding to the most significant bit, and the digital input signal is moved from [01111ill] to ( 10000000
), the linearity of the D/A conversion output cannot be maintained. From the highest side to the lowest side [0111111
In order to maintain linearity when changing from 1) to []OO'00000], even if the relative error of the resistance values of resistors other than resistor 109 is zero, the relative error of resistor 109 must be 0.4% or less. No.

In integrated circuits, it is difficult to reduce the relative accuracy to 0.4% or less, so accuracy is obtained by trimming the resistors.

In particular, in a servo device, the linearity of the D/A conversion output near the center of the r5/A converter is important and plays a major role in determining the performance of the servo device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a D/A converter that has a simple configuration and has good linearity near the center of the D/A conversion output.

(Means for Solving the Problems) The D/A converter of the present invention corresponds to the L-bit first D/A converter and the M-th bit from the lowest order of the first D/A converter. a second N-bit D/A converter whose output value is a maximum value; a digital input signal control circuit that controls digital signals input to the first and second D/A converters; , and an adder circuit that adds the outputs of the second D/A converter.

(Function) According to the present invention, the linearity near the center of the output of the D/A converter is determined by the output characteristics of the second D/A converter, and the linearity of the output of the D/A converter is determined by the output characteristics of the second D/A converter. By making the number of bits smaller than the number of bits of the first D/A converter, it is easier to obtain the linearity of the second D/A converter, and the linearity near the center of the D/A converter is improved. are doing.

(Embodiment) A D/A converter according to an embodiment of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 shows the basic configuration of the D/A converter of the present invention. 1. la are the first and second reference voltage sources, respectively, and if the voltage value of the first reference voltage source 1 is E, the voltage value of the second reference voltage source 1a is 16/256*E. 10
0 is a first ladder resistance network consisting of resistors 101 to 107 with the same resistance value 2R and resistors 108 to 111 with the same resistance value R, and 200 is the first ladder resistance network 10.
A first switch circuit group consisting of switches 201 to 205 connected to one end of each resistor 101 to 105 weighted with 0, 300 is a resistor 30 with the same resistance value 2R.
Resistors 307 to 3 with the same resistance value R as 1 to 306
09, 400 each weighted resistor 301 of the second ladder resistance network 300;
A second switch circuit group consisting of switches 401 to 404 connected to one end of switches 401 to 304, 2 to 9 are digital signal input terminals, 2 being the most significant side and 9 being the least significant side. 500 is a digital input signal control circuit to which digital signal input terminals 2 to 6 are connected. No output terminal 515 of digital input signal control circuit 500 51
9 connects the switches 201 to 205 to the first reference voltage source 1 or to the ground side. Also,
An output signal from the output terminal 520 of the digital input signal control circuit 500 causes the switch 401 to switch to the second reference voltage source 1.
a, or connected to the ground side. Switch 402 is activated by digital signals from digital signal input terminals 7 to 9.
404 are connected to the second reference voltage source 1a or the ground side. 10.14 are operational amplifiers that amplify the D/A conversion output, 11.15 are feedback resistors of the operational amplifiers 10.14 each having a resistance value of 3R, and 12.16 are each for offset compensation of the operational amplifiers 10.14. A resistor 17 is an adder circuit for adding the outputs of the operational amplifiers 10 and 14, and 18 is an output terminal of the adder circuit 17. 600 is a first reference voltage source 1, a first load resistance network 100,
A first D consisting of a first switch circuit group 200, an operational amplifier 10, a feedback resistor 11, and an offset compensation resistor 12.
/A converter 700 includes a second reference voltage source 1a, a second ladder resistance network 300, a second switch circuit group 400,
Operational amplifier 14. This is a second D/A converter consisting of a feedback resistor 15 and an offset compensation resistor 16.

FIG. 2 shows a specific example of the digital signal input signal control circuit 500. In the figure, 501 to 505 are
507 is an inverter whose respective input terminals are connected to digital signal input terminals 2 to 6; 506 is a NAND gate whose input terminals are connected to digital signal input terminal 2 and the output terminals of inverters 502 to 505;
is the digital signal input terminal 3 to 6 and the inverter 50
1 is a NAND gate whose output terminal is connected to the input terminal, 508 is an AND gate whose output terminals of NAND gates 506 and 507 are connected to the input terminal, and 509 is an A
AND gates 510 to 513 have the output terminal of the ND gate 508 and the digital signal input terminal 2 connected to their input terminals, and the output terminals of the AND gate 508 are connected to their respective first input terminals, and the output terminals of the AND gate 508 are connected to their second input terminals, respectively. N to which the output terminals of inverters 502 to 505 are connected
AND game 1-1514 has NAND gate 5 on the input terminal.
This is an inverter to which the output terminal of 06 is connected. AND
Gate 509. Output terminals of NAND gates 510 to 513 and inverter 514 are connected to output terminals 515 to 520 of digital input signal control circuit 500.

Regarding the D/A converter configured as above, the following is the first part.
The operation will be explained using FIG.

FIG. 1 shows the basic configuration of the D/A converter of the present invention, and the first D/A converter 600 receives the upper 5-bit digital signal output from the digital input signal control circuit 500. Perform D/A conversion.

The second D/A converter 700 receives the lower 3 bits of the digital input signal inputted to the digital signal input terminals 7 to 9 and the output terminal of the digital input signal control circuit 500 corresponding to the 4th bit from the lowest order side. 4 bits of the 520 digital signal are D/A converted. 1st and 2nd D/A
The D/A converted outputs of the converters 600 and 700 are added together in the adder circuit 17 and output from the D/A conversion output terminal 18 as a D/A conversion output.

The digital input signal control circuit shown in FIG. 519 (0
1111]. Further, when the digital input signal is other than the above, the digital input signal inputted to the digital signal input terminals 2 to 6 is directly applied to the output terminals 515 to 519 of the digital input signal control circuit 500, and the digital input signal control circuit 500 The output terminal 520 of remains at a low level. The output terminal 520 of the digital input signal control circuit 500 becomes high level when digital signal input terminal 2 is high level and digital signal input terminals 3 to 6 are low level.

FIG. 3 shows the D/A conversion characteristics of the D/A converter of the present invention. FIG. 3(a) shows the D/A converter 600.
A conversion characteristics, (b) is the second D/A converter 700
This is the D/A conversion characteristic of

The input of the first D/A converter 600 is as follows:
01111) to [10000] is fixed to (01111) by the digital input signal control circuit 500, so a constant value is output. In addition, in cases other than the above, the input signal from the most significant bit to the fifth bit is the same as the signal input to the digital signal input terminals 2 to 6, so it essentially becomes a D/A converter for the most significant five bits.

The digital signal input terminals 7 to 9 and the output terminal 520 of the digital input signal control circuit 500 are connected to the input terminal of the second D/A converter 700. Since the output terminal 520 of 500 is at low level, the second D/A converter 7
00 operates as a D/A converter for the lower 3 bits. However, in the above section, the digital input signal control circuit 50
The zero output terminal 520 becomes the inverter output of the NAND gate 506, and the second D/A converter 700 becomes a 4-bit D/A converter. For example, input [10000000] to the digital signal input terminal from the highest level to the lowest level.
] is input, a 5-bit digital signal [01111) is input to the first D/A converter 600 by the digital input signal control circuit 500, so a value corresponding to the digital oil number (01111) is inputted to the first D/A converter 600. output and the second D/
The A converter 700 includes a digital input signal control circuit 500.
Since the output terminal 520 of is at high level and the input signals of digital signal input terminals 7 to 9 are at low level, a value corresponding to the digital signal (1000) is output. Here, the maximum output value of the second D/A converter 700 is the maximum output value of the first D/A converter 700.
/A converter 600 corresponds to the output value of the second bit from the least significant side, so the summed output of the first D/A converter 600 and the second D/A converter 700 is a digital input signal. The sum of [01111000) and [00001,000),
That is, it becomes [10000000], which is the same as if a digital input signal (10000000) was input. Therefore, in the interval from [011, 11] to [10000] in which the upper five bits of the digital signal input terminal go from the most significant side to the least significant side, the first D/A converter 600
converts the upper 5 bits of the fixed value [01111], the second D/A converter 700 converts the lower 4 bits, and the first D/A converter 700 converts the lower 4 bits.
By adding the output of the /A converter 600 and the output of the second D/A converter 700, an 8-bit D/A conversion output is obtained. Furthermore, when a digital signal of [01111111,) is input to the digital signal input terminal from the most significant side to the least significant side, the first D/A converter 600 outputs an output value corresponding to the 1st-order 5 bits. is 120/256*
Outputs E. Since the output terminal 520 of the digital input signal control circuit 500 is at a low level, the second D/A converter 700 outputs a digital signal of (01
11), which is an output value corresponding to 7/256 ridges.

Adding the output values of the first and second D/A converters 600 and 700 gives 127/256*E, which is the D/A conversion output corresponding to the digital signal input [01111111]. Furthermore, when a digital signal of [10000000) is input to the digital signal input terminal from the highest side to the lowest side, the first D/A converter 600 receives the digital input signal from the digital input signal control circuit 500. Therefore, 120/256*E is output since it becomes (0111) from the most significant side to the least significant side. Since the output terminal 520 of the digital signal input terminal 500 is at a high level, the second D/A converter 700 outputs a 9/256 signal corresponding to the digital signal (1001) of the lower 4 bits.
Outputs 18. Therefore, by adding the outputs of the first and second D/A converters, the result is 129/2561E, and a D/A conversion output corresponding to the digital signal input (10000001) can be obtained.

In other words, the digital input signal that degrades the linearity of the D/A converter the most is from (01111111) to [
10000000) depends on the linearity of the output of the second D/A converter 700, which is composed of 4 bits, so in order to obtain linearity near the center of D/A conversion, , it is sufficient to ensure the accuracy of the 4-bit D/A converter. In this embodiment, the digital signal input is (0
The linearity of the D/A conversion output is ensured in the range from (1111000) to (10000111).By the way,
In order to obtain the characteristics of a 4-bit D/A converter, it is sufficient to suppress the relative accuracy of the resistance of the most significant bit to 4% or less, and the configuration is much easier than in the case of 8 bits.

As described above, according to this embodiment, the first D/A converter 60 which performs D/A conversion on the upper 5 bits near the center
The second D/A converter 7 fixes the digital input signal of 0 to (01111) and converts the lower 4 bits into D/A.
By utilizing the characteristic of good linearity of the output of 00, it is possible to improve the linearity near the center of D/A conversion.

(Effects of the Invention) According to the present invention, the output values corresponding to the L-bit first D/A converter and the M-th bit from the lowest order of the first D/A converter have the maximum value N a second D/A converter of bits;
A control circuit that controls the digital signals input to the first and second D/A converters, and an adder circuit that adds the analog outputs of the first and second D/A converters, M+1
) bit by configuring a D/A converter.
This has the effect of easily obtaining linearity of the D/A conversion characteristics near the center of the converter.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a D/A converter according to an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the digital input signal control circuit of FIG. 1, and FIG. FIG. 4 is a diagram showing the conversion characteristics of a D/A converter, and is a basic configuration diagram of a conventional D/A converter. 1.1a... Reference voltage source, 2 to 9... Digital signal input terminal, 10.14... Operational amplifier, 1
1.15... Feedback resistor, 12, 1.6... Compensation resistor, 17... Adder circuit, 18... D/A conversion output terminal, 100.300... Ladder resistance network, 101 to 111.301 to 309... Resistance, 200,
400...Switch circuit group, 201 to 208, 4
01 to 404... Switch, 500... Digital input signal control circuit, 515 to 519... Output signal, 520... Output terminal, 600... First D/
A converter, 700... second D/A converter. Figure 3 (a) Figure 3 (b)

Claims (3)

[Claims] (1) Corresponds to the first digital-to-analog converter of L bits (L is an integer) and the Mth bit (M is an integer, L>M≧2) from the lowest order of the first digital-to-analog converter. a second digital-to-analog converter of N bits (N is an integer) whose output value is a maximum value; and digital input signal control for controlling digital signals input to the first and second digital-to-analog converters. and an addition circuit for adding the analog outputs of the first and second digital-to-analog converters (L+N-M
+1) bit digital-to-analog converter. (2) Claim (1) characterized in that the number M of bits from the lowest order of the first digital-analog converter is smaller than the number N of bits of the second digital-analog converter. digital-to-analog converter. (3) When the input signal of the most significant bit of the first digital-to-analog converter is high level and the input signals of other bits are low level, the digital input signal control circuit receives the input signal of the most significant bit. is low level and the input signals of other bits are high level, the input signals of the first digital-to-analog converter are set so that the input signal of the most significant bit is set to low level and the input signal of other bits is set to high level. , the upper part of the second digital-to-analog converter (M-1
) bit input signal is controlled to be the same signal as the most significant bit of the digital input signal, and at times other than the above, the input signal of the upper (M-1) bits of the second digital-to-analog converter is set to a low level. A digital-to-analog converter according to claim 1, characterized in that the digital-to-analog converter is controlled.